Bob Cordell's Power amplifier book

If you have transistors that fT below 100MHz, a 100MHz+ scope should be able to see it.

The trick I used a lot when I was working with transistor with fT over 1GHz, you cannot see the oscillation with a 400MHz scope, but you can look at the output offset. I called it a pencil or screw driver test. Using a pencil or screw driver and touch around, you'll see the offset jump. It's like touching a raw nerve and the thing jump!!! In the 80s, nobody had 1GHz+ scope, you just adapt. You see enough, you can tell. First thing first is to poke around and look for raw nerve if you don't see oscillation with a slower scope.

If there is no oscillation problems, the circuits in text books really work and it's that easy. What make engineers earn their keeps is the ability of taming oscillations. It's a routine thing to tame oscillation in circuit design!!! I just encountered oscillation in the most unexpected place in my contract work. The voltage regulator enable input cause the regulator to oscillate even if it is a quasi logic level input. It showed up in the sensitive amplifier output and fooled me for an hour before I chased it down. It's a day to day thing!!! This just happened day before yesterday. Data sheet never flag precaution on that!!!

I learned this pencil technique when I was working with LeCroy in the 80s, opamps were slow, we had to design hybrid opamps using BFR90 or 91 RF transistors inside a DIP package. Oscillation was always a problem, I think it was even Walter LeCroy that taught me this trick.

Layout is everything, the war is won or loss on the layout. That's the reason I started with a solid power and ground planes with 0.1uF and 10uF bypass transistor on every single collector of the EF transistor. This technique might not work for GHz transistor as the loss of the capacitor comes into play. But this work every time on the slow transistors. The circuit pcb is designed to be good to over 100MHz. Base stop works.

BUT, what if the probe causes oscillation, rather than stops it? This could easily be true as the screwdriver couples to another node and causes a feedback loop, or it could simply load a node with the right phase to cause oscillation. It seems that this technique might exclude many useful circuits.
 
BUT, what if the probe causes oscillation, rather than stops it? This could easily be true as the screwdriver couples to another node and causes a feedback loop, or it could simply load a node with the right phase to cause oscillation. It seems that this technique might exclude many useful circuits.

For low speed circuit, a pencil or screw driver are not going to do much. If it oscillates upon touching, you don't have enough stability margin to start with and needs to be fixed. I never encounter a case that a low speed circuit is not oscillating and it start oscillate when I touch something. I can only tell you that it never fail me all these years. This is the poor man's way of working with transistors beyond the speed of your test equipment. I did not invent this, it's taught by Walter Lecroy, the founder of LeCroy digital scope company. I worked directly under him in 1982 on a digitizer and I had to travel to NJ to meet him.

But in any case, for transistors below 100MHz like the ones we are talking here, you can see oscillation on the scope unless you have a very slow scope. A 100MHz scope is only about $200 or less if you get it in surplus store. I hold on to my Tek 465 as it is one of the best scope. I used 475 and 2465, the 465 still the best if you don't need very wide band.

MOSFET are more dangerous, when they oscillate, they usually die before you can even touch or test it. Most of the time, they die a quiet death, no heat, no bang, just stop working. If you measure, all the leads shorted out. I believe the gate and drain forms a tank circuit inside and oscillate with enough voltage to punch through the gate and die.
 
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I have tried, but without success, a reverse method.
I see a bit of ringing on the output.

I had assumed that some parasitic was bringing the circuit close to unstable and that a bit extra would push it "over the edge".

I go around touching various nodes, or transistor leads, to see if I can get the ringing to change either for the worse, or better. but it did not locate the source of the ringing.
Told you I'm not much good at this AC stuff.
 
For audio amp, I don't think it's that sensitive to touch. Also, try sweeping the generator up the frequency and look at the waveform to see whether the it transition to some strange shape, or some high frequency modulating on the sine wave at some frequency. Or shape change very sudden. I found when the circuit is conditionally stable, strange things happen when you sweep frequency, pulse with square wave or touching it.

I don't know how better can I describe it, it's like touching raw nerve, it jump or transition very sudden if there is parasitic problem. Or you can see the frequency of oscillation changes when you touch it. You know you are closing in. If everything change very gradually, and predictably, good chance it's stable.

That's how I found and fix the oscillation due to the diamond configuration on my OPS, I stick the screw driver around, when I only see amplitude changes but frequency stays the same, I know I am not at the nerve yet. I poked around to the point that the frequency changes, I know I am getting close. The other tell tale is when I change the length of the input coax, the frequency changes. I know right away that the problem is at the input area. turn out the Ccb of the pre driver is feeding back signal from the driver to the input.
 
OS probably could have told you about the Ccb. On EF designs RC decoupling between EF stages is highly beneficial to stability. In this sense diamond predrivers aren't any different.

I have also had the problem where a lytic was paralleled by a 100nF or so film cap, causing the rails to ring, which would show up in the output because of PSRR, and could also cause oscillation. Often those 100nF decouplers are not really necessary or even helpful.
 
I have tried, but without success, a reverse method.
I see a bit of ringing on the output.

I had assumed that some parasitic was bringing the circuit close to unstable and that a bit extra would push it "over the edge".

I go around touching various nodes, or transistor leads, to see if I can get the ringing to change either for the worse, or better. but it did not locate the source of the ringing.
Told you I'm not much good at this AC stuff.

Specific circuit designs can have nodes with high enough impedance that this can be a problem. Not anything I've seen on DIYAudio though. Sometimes your output may be statically coupling to the input which can cause ringing if you don't have a 220pF input decoupler or your input is unconnected and not shorted to ground.

When you get ringing like you describe, it can be because your simulation transistor model was bad or was a model for a different manufacturer (Motorola/OnSemi and Fairchild can be different enough that it will make a difference in certain circuits).

I have a design where the stability compensation is a 5pF capacitor to ground from an extremely high impedance VAS! Understandably I was worried about the prototype, so I never tried it (probably possible to do, just a bit tedious).
 
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OS probably could have told you about the Ccb. On EF designs RC decoupling between EF stages is highly beneficial to stability. In this sense diamond predrivers aren't any different.

I have also had the problem where a lytic was paralleled by a 100nF or so film cap, causing the rails to ring, which would show up in the output because of PSRR, and could also cause oscillation. Often those 100nF decouplers are not really necessary or even helpful.

What is OS, you mean Ostripper the person here?

What do you mean by RC decoupling between EF stage?

No Diamond driver is totally different. If you read this:http://www.diyaudio.com/forums/solid-state/278494-issue-3ef-diamond.html, I explained in detail my theory and way to fix it. It is totally different from the local parasitic oscillation that we have been talking so far. I asked Mr. Cordell his opinion, he never answered. The tell tale is the frequency is too low for simple local oscillation of a single transistor. I expect frequency will be closer to fT for single transistor local oscillation caused by parasitic.

About decoupling with 0.1 parallel with 10uF. This is where I really have different opinion. You might have problem like you described if you don't have a good ground plane(preferably) power plane. Then you have parasitic inductance of the trace, long ground current loop that causes EM radiation, creating parasitic elements and all. It is not an option for me when I layout my pcb that I do everything possible to have at least a ground plane, if possible, power planes. You minimize or eliminate parasitic inductance with healthy planes. Then you put 0.1 and 10uF point to point from the collector of the EF to the ground. For slow transistor we are talking here, you really make the true circuit behaving like what you draw on the schematic where the collector connects to the rail that is AC grounded to the ground. Just like the simplified drawing that the collector is connected to the ground. But of cause, I know most of the people here don't believe in ground planes, this is another debate for another day.
 
Yes, I meant OStripper.

We are in complete agreement on (intelligent) ground planes and layout. I was actually quite interested in your PCB layout, it is what I have always wanted to do. 100nF in parallel with 10uF I don't have much of a problem with. But 100uF and up I start to worry.

I did not mean local parasitic oscillation. I mean positive feedback from proceeding collectors to preceding Ccb. An RC filter separating them is effective against this. Maybe you should ask in the Slewmaster thread, that is OStripper's domain.
 
When you get ringing like you describe, it can be because your simulation transistor model was bad or was a model for a different manufacturer (Motorola/OnSemi and Fairchild can be different enough that it will make a difference in certain circuits).

Don't trust simulation totally. In fact I am invited to go to Linear Technology next week by their application engineer to work together on the circuit of my contract job. My contract is to push the limit of a transimpedance amplify design to have 100MV/A transimpedance gain and settle to 0.1% under 5uS. I chose their LTC6268 and I had be communicating to Glen Brisebois in LT from the beginning. He is the one that wrote the test and application circuit for that opamp. In the LTSpice simulation, I can achieve the goal, but when I have to real board, I can't get the settling time under 50uS. I show him my layout and what I did with pictures, the precautions I took on the layout. He cannot understand why I don't get close to the simulation, so he invited me to go to LT to work together. He even said I should get at least half the speed as in the simulation.....which is understandable, because no matter how careful and how much I do to lower the parasitic in the layout, I will never eliminate it. But not 10 times slower.

Believe it or not, this will be the second time I go to LT already. They invited me in the first time to show them a power up problem of on of their IC that it latched up on power up. They were red faced and gave me quite a few of the IC and promised to fix that.
 
If you can calculate it by hand, a simulator can do it. The simulator might have a problem in the model. I once found a bug in LTSpice concerning the Ft in quasi-saturation of a BJT in AC analysis. It happens. Usually someone who understands what they're doing can figure out when the simulator is wrong by fact-checking.
 
the 1st shows anti-resonance peaks with the bypass a big cap with smaller plan

the 2nd assumes massive paralleling identical small caps, gives some layout, implementation parasitic L numbers

I've looked into bypassing in ADC precision instrumentaiton applications - there are newer low inductance SMT "wide" termination caps and multi-terminal types for multi-MHz work - you're bascially screwed if you have to use through-hole parts

there is some info on what really happens in bypass applications and random paralleling of different caps can result in impedance peaks in the supply impedance
http://www.ultracad.com/articles/esrbcap.pdf shows the "anti-resonance" impedance peak you can get with the wrong choice of caps in parallel

http://www.pa.msu.edu/hep/d0/ftp/ru...nformation/xilinx_xapp623_decoupling_caps.pdf

also shows measured ps impedance peaking


the plots show ESR isn't always bad - lowers impecance peaking even if ultimate low Z is limited - sometimes introducing discrete R is a good idea
 
Yes, I meant OStripper.

We are in complete agreement on (intelligent) ground planes and layout. I was actually quite interested in your PCB layout, it is what I have always wanted to do. 100nF in parallel with 10uF I don't have much of a problem with. But 100uF and up I start to worry.

I did not mean local parasitic oscillation. I mean positive feedback from proceeding collectors to preceding Ccb. An RC filter separating them is effective against this. Maybe you should ask in the Slewmaster thread, that is OStripper's domain.


I know there is a lot of talks about parallel caps. I did challenge this in this thread: http://www.diyaudio.com/forums/parts/278536-why-dont-people-stack-lower-voltage-filter-caps-6.html , Read my post #52 onward. Actually the person that wrote the paper was on that thread, but he did not rebut my finding. You have to be careful what is being said, even in books. Always challenge, always ask why. If it is important enough, put in the effort to verify. It is my believe on paralleling caps of 100:1 ratio, so I studied his paper and did my homework.

I know I am disliked by a lot of people here keep asking why, but to me, that's the way people learn. A theory is true ONLY if it cannot be challenged. People should never take what is written 100%. As I wrote in this thread many times, I verify a lot of the formulas of Mr. Cordell's book. I really respect him because he is spot on with the formulas.

Grounding and signal integrity is another thing that I am very passionate about. There is another thread that I defended my grounding scheme where everyone said I was wrong. http://www.diyaudio.com/forums/solid-state/277695-grounding-issues-integrated-amp-9.html If you are interested, start reading from post #83 I put my grounding scheme in LTSpice and did the simulation. I showed very good result. I just let people challenge it. I am willing to be wrong, just show me.

To me, this is a productive way of learning. If I am proven wrong, I am wrong. I think it would be more productive if people don't take challenge as offensive. That's how we learn. Never take people's word 100%, always verify.
 
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Hi Alan0354,
I know I am disliked by a lot of people here keep asking why, but to me, that's the way people learn.
Ever hear of the phrase "within reason"?
When you take a discussion off its path, that is called "thread jacking". Don't do it.
When you dive into your own specific problem to the exclusion of all others, that's a form of thread jacking. If you argue with a skilled person who has more experience and skill than you have, stopping the thread, that is just plain selfish.

Basically, anything you may do that diverts the course and discussion on a thread, you are negatively affecting everyone who has invested time and have been learning. If the topic you want to find out more on will take more than a few posts, or completely interrupt other members, you should begin your own thread. Not to do this is strongly ignorant of the needs and activities of everyone else participating in that thread.

It's like that kid at the front of the class in university who always has his hand up. Taking over the lesson to the point where the material can not be finished. That is not what a class is for to begin with. You are shown the material. If you can't keep up, or have extra questions, you research it and study on your own. Then you can contact the authority(ies) in that thread to ask an intelligent question. Or you start your own thread, or contact them via email. What you do not do is interfere with what is going on in a thread. There are exclusions, like is something dangerous being advocated, or the argument is fundamentally unsound to begin with - conflicting with well known facts.

These are things that are the most annoying to everyone, and yes. People will begin to hate it when you show up on a thread. Many leave, and I have seen the principles of a discussion give up and leave the thread. So you see, doing those things robs people of what they were learning to satisfy your own desire for a one-on-one education. It is rude, selfish and self-centered. Do not do this. No one owes you an education, nor is it acceptable to take over a thread for your own pleasure, learning or otherwise.

-Chris
 
"If I am proven wrong, I am wrong. I think it would be more productive if people don't take challenge as offensive. That's how we learn. Never take people's word 100%, always verify."

Alan,
I for one find this very relevant in anything I have done, not just electronics but in every other field. Never just take someone's word for it, check it out and make your own determination. Many times these rules that others give you are not correct, they only worked in a specific case and fall apart when closely analyzed.

 
Still in agreement, with the exception that a 10uF MKT is still gonna ring with a 10nF ceramic even though it fits in your 100:1 rule.

Like Anatech says though, maybe you should start your own thread rather than being so offended by some people who didn't trust your design philosophy. I for one would be an eager participant, I'd like to learn more about RF design from you, I'm sure others are interested too.
 
Hi Alan0354,

Ever hear of the phrase "within reason"?...............
-Chris

I did not start the long discussion about oscillation and all. I started on asking Mr. Cordell about the low voltage spreader using CFP. Someone said it can be from local oscillation and I answered it's not. That's how the whole thing started. Threads has their ways to get off subject. If I just stop at that point, I'll never get back to the CFP. Mr. Cordell told me to give my theory which I did and I want to hear what he say.

And to be blunt, I am tired of people keep telling me I don't know enough and just sit back and learn. I might be new in this, but I have been around electronics for 30 years, I think I have a lot of experience in electronics that is very relevant to electronics in audiophile. Layout and parasitic is not limited to audio amps, it is a major topic that has been well studied and published outside of audiophile.
 
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Still in agreement, with the exception that a 10uF MKT is still gonna ring with a 10nF ceramic even though it fits in your 100:1 rule.

Like Anatech says though, maybe you should start your own thread rather than being so offended by some people who didn't trust your design philosophy. I for one would be an eager participant, I'd like to learn more about RF design from you, I'm sure others are interested too.

I generally use a 100uF electrolytic in parallel with a 0.1uF film capacitor.

The ESR of the electrolytic is key to damping out any resonance.

Note also that it is wise to bypass the feedback shunt decoupling electrolytic with a film capacitor.

Cheers,
Bob