I did a quick simulation in LTSpice with a three stage Class AB amplifier with a two pair CFP output stage using 0.1Ω emitter resistors. Based on the simulation, there is a small effect on distortion. I compared it against matched values scenarios that were 5% high or low to factor out any differences from the change in absolute value. Bias levels were adjusted in the matched high and low scenarios to eliminate distortion changes due to bias changes.
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Interesting results. Could you possibly check what would happen if the beta was increased by 50 in all tests except for the first baseline measurement.
This may help understand what may happen when using the MJL4281A/MJL4302A
I should have mentioned that the simulation I ran this under uses lateral MOSFETs. A design I've been tinkering with.
It might be interesting to run this again with a BJT OPS and with CFP vs EF to see how they compare. I could also try Bob's various models (4281/4302, 3281/1302 and 21193/21194) along with different absolute emitter resistor values (0.1, 0.22, 0.33).
Just for fun. Looks like a busy evening tonight
It might be interesting to run this again with a BJT OPS and with CFP vs EF to see how they compare. I could also try Bob's various models (4281/4302, 3281/1302 and 21193/21194) along with different absolute emitter resistor values (0.1, 0.22, 0.33).
Just for fun. Looks like a busy evening tonight
I switched over to a simple version of the Douglas Self's blameless load invariant. I ran the analysis with 0.1R and 0.33R emitter resistors at various frequencies and output levels with 1202/3281 and 21193/21194 output devices.
Interesting result. Green highlighting indicates the lowest distortion level for each test. I don't think there's anything conclusive to gleam. Unless the approach or file I'm using is flawed. I attached the LTSpice asc files in case anyone else wants to tinker (or find those flaws).
Interesting result. Green highlighting indicates the lowest distortion level for each test. I don't think there's anything conclusive to gleam. Unless the approach or file I'm using is flawed. I attached the LTSpice asc files in case anyone else wants to tinker (or find those flaws).
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Output stage is misbehaving
There are pretty significant turn-on/turn-off artifacts in the output stage that are causing crossover distortion. I show these, and the FFT. I like seeing the FFT because that gives more hints about what is going on than just a THD number.
There are pretty significant turn-on/turn-off artifacts in the output stage that are causing crossover distortion. I show these, and the FFT. I like seeing the FFT because that gives more hints about what is going on than just a THD number.
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Since I have a bit of time, I'll pitch in:
From Keantoken:
The "actual transfer function" is not singularly important as the phrase suggests. What is important is how distortions, originating in current or voltage, enter the drive current required from the input stage to make the amp work. In one topology the voltage transfer function is important. In another, the current gain function is important.
That is exactly right, specially the second sentence... I am very impressed. You should be proud, only the few truly understand that. The formula for output distortion is:
VO_Distortion = Io_ips_error / GM_ips * Acl
where, Io_ips_error is the error current coming out of the input stage due to a distortion artifact, GM_IPS is the GM of the input stage, and Acl is the amplifier's gain.
If you prefer RTI, then no need to multiply by Acl.
IO_IPS_error is a consequence of every single distortion in the amp. YES, every distortion mechanism can be mapped to IO_IPS_error and then its distortion contribution can be calculated with the formula above. It is the skill of the circuit designer to figure out how the mapping happens.
Here is my favorite example:
- Say the error voltage of the output stage is VE. That causes a current in the Miller cap CM of IE = VE * s * CM = IO_IPS_error
- Therefore, the output distortion is :
VO_Distortion = VE * s * CM / GM_IPS * Acl = VE / (GM_IPS / (s*CM)) * Acl
- Now, GM_IPS/ (s * CM) is the open loop gain of the amp AOL, such that
VO_Distortion = VE / AOL * Acl
This is why 'the books' say that the output stage voltage error gets divided down by the amp open loop gain.
From Bob:
Yes, base stopper resistors definitely act as if part of the emitter resistor in an output stage. Their presence, if large (10 ohms is large) also degrades thermal stability in regard to current hogging with paralleled output transistors.
This is wrong. It is the other way round. Base stopper resistors improve the thermal stability, provided every pair has them. If a transistor tries to hog the current, base current increased, which increases the voltage across the base stopper which decreases VBE. Negative feedback.
Brian92fs:
As your sims confirm, the effect of RE mismatch should be neglible given that the current across them should be linear when the output device is active.
From Keantoken:
The "actual transfer function" is not singularly important as the phrase suggests. What is important is how distortions, originating in current or voltage, enter the drive current required from the input stage to make the amp work. In one topology the voltage transfer function is important. In another, the current gain function is important.
That is exactly right, specially the second sentence... I am very impressed. You should be proud, only the few truly understand that. The formula for output distortion is:
VO_Distortion = Io_ips_error / GM_ips * Acl
where, Io_ips_error is the error current coming out of the input stage due to a distortion artifact, GM_IPS is the GM of the input stage, and Acl is the amplifier's gain.
If you prefer RTI, then no need to multiply by Acl.
IO_IPS_error is a consequence of every single distortion in the amp. YES, every distortion mechanism can be mapped to IO_IPS_error and then its distortion contribution can be calculated with the formula above. It is the skill of the circuit designer to figure out how the mapping happens.
Here is my favorite example:
- Say the error voltage of the output stage is VE. That causes a current in the Miller cap CM of IE = VE * s * CM = IO_IPS_error
- Therefore, the output distortion is :
VO_Distortion = VE * s * CM / GM_IPS * Acl = VE / (GM_IPS / (s*CM)) * Acl
- Now, GM_IPS/ (s * CM) is the open loop gain of the amp AOL, such that
VO_Distortion = VE / AOL * Acl
This is why 'the books' say that the output stage voltage error gets divided down by the amp open loop gain.
From Bob:
Yes, base stopper resistors definitely act as if part of the emitter resistor in an output stage. Their presence, if large (10 ohms is large) also degrades thermal stability in regard to current hogging with paralleled output transistors.
This is wrong. It is the other way round. Base stopper resistors improve the thermal stability, provided every pair has them. If a transistor tries to hog the current, base current increased, which increases the voltage across the base stopper which decreases VBE. Negative feedback.
Brian92fs:
As your sims confirm, the effect of RE mismatch should be neglible given that the current across them should be linear when the output device is active.
Almost good. Take into consideration, that the hfe increases as the transistor's temperature increases. So the base current will not follow the emitter current proportionally. The emitter resistor gives better negative feedback for the bias.
No, Bob is exactly right. Beta mismatch will be magnified by the base stopper resistors. Base resistors directly convert beta mismatch into Vbe mismatch, causing Ic mismatch to be even worse. Thermally, beta rises with temperature, and excessive base stop resistance would contribute to thermal hogging. In the classic bias stability equations, high Re and low Rb give the best stability.
If we are sticking to the Oliver criteria, that means that regardless of what base resistor we use, the transconductance will be the same value. So in our scenario (the amp on our bench, as it were) Rb does not decrease Gm because any decrease caused by Rb is made up by decreasing Re. So Sandro's argument doesn't hold unless you throw out the Oliver criteria (he is not entirely wrong however).
Taking transconductance as invariant of Rb due to the Oliver criteria, and knowing that Ic tempco determines thermal gain, we only need to work out the contribution of both Rb and Vbe to the voltage tempco that appears across the transconductance.
The MJL3281 very roughly has a 18ppm Hfe tempco based on the datasheet. At 100mA that means 18uA per C or 18uV per C per ohm Rb. Vbe tempco is 1.8mV per C, so to match that tempco you need 1.8mV/18uV or 100 ohms of base resistance.
Even if we satisfy the Oliver criteria entirely with base resistance, with a 25 ohm base resistor, we are only adding -450uV/C to the -1.8mV/C tempco of Vbe. At a more typical Rb of 5 ohms we are only increasing the tempco by 5%. The PNP has a worse tempco but it also gets a smaller base resistor since it's slower.
So Sandro's argument holds if you don't maintain the Oliver criteria by decreasing the emitter resistor as you increase Rb. If you stick to the Oliver criteria though, Rb has a minor negative effect on thermal hogging which could be important if you end up having to use large base resistors and your thermal insulators aren't very good or you are using high Vce.
Taking transconductance as invariant of Rb due to the Oliver criteria, and knowing that Ic tempco determines thermal gain, we only need to work out the contribution of both Rb and Vbe to the voltage tempco that appears across the transconductance.
The MJL3281 very roughly has a 18ppm Hfe tempco based on the datasheet. At 100mA that means 18uA per C or 18uV per C per ohm Rb. Vbe tempco is 1.8mV per C, so to match that tempco you need 1.8mV/18uV or 100 ohms of base resistance.
Even if we satisfy the Oliver criteria entirely with base resistance, with a 25 ohm base resistor, we are only adding -450uV/C to the -1.8mV/C tempco of Vbe. At a more typical Rb of 5 ohms we are only increasing the tempco by 5%. The PNP has a worse tempco but it also gets a smaller base resistor since it's slower.
So Sandro's argument holds if you don't maintain the Oliver criteria by decreasing the emitter resistor as you increase Rb. If you stick to the Oliver criteria though, Rb has a minor negative effect on thermal hogging which could be important if you end up having to use large base resistors and your thermal insulators aren't very good or you are using high Vce.
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The Oliver voltage can vary over quite a range. It’s quite a flat, bathtub shape. I usually use 0.33 ohm emitter degen resistors and minimum distortion (ie lowest) is flat from <30 mA all the way up to 90mA. The distortion on a big EF3 amp sans error correction was measured at around 30 ppm max at 200W into 8 Ohms over this standing current range with a QA401.
So, I think there is quite some leeway in the Oliver voltage to play with to balance the requirements of lowest distortion and thermal stability.
Maybe others have a different experience - be interested to hear of their findings.
(NB I also always use 4.7 Ohm base stoppers)
So, I think there is quite some leeway in the Oliver voltage to play with to balance the requirements of lowest distortion and thermal stability.
Maybe others have a different experience - be interested to hear of their findings.
(NB I also always use 4.7 Ohm base stoppers)
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Do you know if that bathtub was filled in with other distortions, since it appears you were measuring the whole amp and not just the output stage contribution to distortion? For that I would measure distortion at the input of the output stage.
If this is the case, then as I said before if you reduced the frontend distortions the OPS distortions would become significant again.
It also matters what output power. At max output power the crossover region is just a small blip at zero crossing and doesn't necessarily contribute much to distortion.
Here is a chart I made in 2014 which is related to the discussion.
If this is the case, then as I said before if you reduced the frontend distortions the OPS distortions would become significant again.
It also matters what output power. At max output power the crossover region is just a small blip at zero crossing and doesn't necessarily contribute much to distortion.
Here is a chart I made in 2014 which is related to the discussion.
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It was total distortion - unfortunately I was not able to separate the different stages out. But, nevertheless, the only point I was making was that it was low so this indeed provides some leeway with the other design parameters.
IIRC, there was another guy a few years back that had a similar result varying the OPS Iq over a large range.
I never measured distortion at very low levels, but it goes down with power until it falls below the instrument noise level which in my set-up with a 100:1 input attenuator is 7 ppm. I cannot tell what’s going on below this level.
IIRC, there was another guy a few years back that had a similar result varying the OPS Iq over a large range.
I never measured distortion at very low levels, but it goes down with power until it falls below the instrument noise level which in my set-up with a 100:1 input attenuator is 7 ppm. I cannot tell what’s going on below this level.
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No, that's simply wrong. Vbe of each transistor is decreased by Rb *(Ic/beta). The high beta devices will have a higher Vbe than the low beta devices. They will get hotter, which gives them an even higher Vbe.
Let's say Rb is 10, beta1 is 100 and beta 2 is 150. Let the bias current per transistor be 100mA.
V(Rb1) = 10mV.
V(Rb2) = 6.7 mV
V(Rb2) = 6.7 mV
That's still not the solution. You have to iterate the equation Vbe = 0.026*ln(Ib/Is). A 2.3 mV change in Vbe causes a 9.2% change in Ic, and that's the first iteration, and I'm assuming the betas stay constant.
For two transistors with the same Vbe @ 100mA, but a beta ratio 150/100, Rb=10 causes the higher beta device to have about 10% more current. Rb is the offender in this instability. This really has nothing to do with the Oliver condition for lowest distortion.
Thanks, Russ.
For those here who have my second edition, this issue is covered succinctly and in a simplified way in Chapter 17, page 407. Your explanation is an even better one.
I realize that these sorts of things are sometimes non-intuitive even to brilliant engineers. One always has to drill down. Intuition makes a good engineer, but it is only a starting point. It will sometimes bite you in the butt, as it has me many times.
Cheers,
Bob
For those here who have my second edition, this issue is covered succinctly and in a simplified way in Chapter 17, page 407. Your explanation is an even better one.
I realize that these sorts of things are sometimes non-intuitive even to brilliant engineers. One always has to drill down. Intuition makes a good engineer, but it is only a starting point. It will sometimes bite you in the butt, as it has me many times.
Cheers,
Bob
Whoops. I made a mistake. That should be a 3.3mV change in Vbe, not 2.3mV.
10-6.7=3.3
change = exp(3.3mV/26mV) = 1.135, or a 13.5% increase in Ic, and after iteration would be about a 15% difference in Ic, due to beta mismatch and Rb. Beta mismatch alone would cause no difference, if Vbe matches at that Ic (by definition).
BTW, Mr. Cordell. I bought your 2nd edition a month ago. It is excellent. Between that and Doug Self's book, there aren't very many aspects of amplifier design that aren't covered. I've been using your pointers, especially on triple-EF stability, to fine-tune my amplifier design posted here:Bob Cordell said:
RK-Auto200W Amplifer
Granted, Hfe mismatch will cause one transistor to have more current.
I am talking about current hogging caused by thermal gain, which is responsible for amplifying an already existing mismatch. One which would be less severe if we were to use the beta controlled output transistors. That is what I mean by thermal stability.
In my view, base resistors do cause a mismatch but it is partly thermal gain which is responsible for that mismatch getting out of control. At normal base resistor values with controlled beta output transistors I'm not sure the mismatch is enough to be be concerning without a large thermal gain.
On a heatsink with good spreading, a single 250W power transistor with 0.22ohm emitter resistors has about 20% differential thermal gain at idle just due to Vbe. Differential as in, relative to the other power transistors as current hogging is a local differential phenomenon. Since Gm doubles at high currents, that increases to 40% at excursions. So any existing mismatch is increased by up to 40% or 1.4x by thermal gain, without even adding in the extra several % coming from Hfe tempco.
So I think thermal gain and static mismatch both play a role here.
You are assuming that the voltage difference appears directly across Vbe and there is no degeneration. At the Oliver null, effective Gm is half that of the BE junction, so your current deltas are half what you calculated. At excursions however Gm approaches that of the transistor's idle value since to satisfy Oliver Re is equal to the idle 1/Gm. So your number is correct at excursions, but there the voltage is applied mostly across the degeneration, not Vbe.
The thermal gain that occurs as you iterate the equation depends on Vbe, Ic tempco and thermal Rjs.
Heat decreases Vbe, This sentence might make sense in context but be wary of writing apparent contradictions.
The increase in Vbe due to the base resistor is less than the decrease in Vbe due to Vbe tempco (both effects increase Ic).
I am talking about current hogging caused by thermal gain, which is responsible for amplifying an already existing mismatch. One which would be less severe if we were to use the beta controlled output transistors. That is what I mean by thermal stability.
In my view, base resistors do cause a mismatch but it is partly thermal gain which is responsible for that mismatch getting out of control. At normal base resistor values with controlled beta output transistors I'm not sure the mismatch is enough to be be concerning without a large thermal gain.
On a heatsink with good spreading, a single 250W power transistor with 0.22ohm emitter resistors has about 20% differential thermal gain at idle just due to Vbe. Differential as in, relative to the other power transistors as current hogging is a local differential phenomenon. Since Gm doubles at high currents, that increases to 40% at excursions. So any existing mismatch is increased by up to 40% or 1.4x by thermal gain, without even adding in the extra several % coming from Hfe tempco.
So I think thermal gain and static mismatch both play a role here.
You are assuming that the voltage difference appears directly across Vbe and there is no degeneration. At the Oliver null, effective Gm is half that of the BE junction, so your current deltas are half what you calculated. At excursions however Gm approaches that of the transistor's idle value since to satisfy Oliver Re is equal to the idle 1/Gm. So your number is correct at excursions, but there the voltage is applied mostly across the degeneration, not Vbe.
The thermal gain that occurs as you iterate the equation depends on Vbe, Ic tempco and thermal Rjs.
Heat decreases Vbe, This sentence might make sense in context but be wary of writing apparent contradictions.
The increase in Vbe due to the base resistor is less than the decrease in Vbe due to Vbe tempco (both effects increase Ic).
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