From post 836
Papa said:
Remember that the thermistors are mostly a convenience. You
can build a fine F5 without them, so there's not too much reason
to get excited about the specific part and such. Having said that,
my preference is to just glue them to the top of the plastic
case on the transistor.
Papa said:
Remember that the thermistors are mostly a convenience. You
can build a fine F5 without them, so there's not too much reason
to get excited about the specific part and such. Having said that,
my preference is to just glue them to the top of the plastic
case on the transistor.
One thing about the Fairchilds -- the diameter of the mounting hole is 3.38mm while that of the Vishay IRFs is 3.68mm -- means that you are gonna be a little tight with a 6-32 screw if you tap your heat sink to mount the devices.
The THD% with the P-Channel replaced is about as low as shown on the chart in the AX article.
The THD% with the P-Channel replaced is about as low as shown on the chart in the AX article.
It's still there -- peak is around 500kHz. The chart below is from the AP -- I allowed it to thermally stabilize -- about 3 hrs:
I checked out my HP network analyzer and the AP to make sure there wasn't some error in the test setup itself. The load is pretty resistive right up to 1 MHz, and there's no wonky stuff in the attenuators, etc.
By using higher value gate-stoppers I could bring the f3 down, but it would be "peakier".
I'm going to change both devices and monkey with the gate stoppers. It would be a shame
An externally hosted image should be here but it was not working when we last tested it.
I checked out my HP network analyzer and the AP to make sure there wasn't some error in the test setup itself. The load is pretty resistive right up to 1 MHz, and there's no wonky stuff in the attenuators, etc.
By using higher value gate-stoppers I could bring the f3 down, but it would be "peakier".
I'm going to change both devices and monkey with the gate stoppers. It would be a shame
steenoe said:
Thats right, nice surroundings for the solder ironThis is how an "English breakfast" looks like on Samos.
That's Pythagorio!
And the boat showing the German flag is the one of the guy from the charter company where we rent our sail in 2006! We used to call him "U-boot" 'cause he looks like an old sailorman from WWIINice shot!
I have found at suiteable heatsink for each channel and the distance between each output MOS-FET will be 20cm. This gives some questions about the physical layout:
1. Do I mount each JFET close to the MOSFET and run wires to the other half?
2. Do I mount the input JFETs close to each other and run wires to the MOSFETs?
a) Do I let each half have its own feedback loop before running the output to output terminal, where the two half meet?
b) Do I connect the drains of the output MOSFET and run this point to the output terminal. And from here take feedback back to input?
My own idea is to use 1b, but is that the best way?
The principle question is where to have short wires and where to run longer...
1. Do I mount each JFET close to the MOSFET and run wires to the other half?
2. Do I mount the input JFETs close to each other and run wires to the MOSFETs?
a) Do I let each half have its own feedback loop before running the output to output terminal, where the two half meet?
b) Do I connect the drains of the output MOSFET and run this point to the output terminal. And from here take feedback back to input?
My own idea is to use 1b, but is that the best way?
The principle question is where to have short wires and where to run longer...
beginner's pcb
This is my second design, if you find any error please advise me or to make the design better. I will release etch layout later if the design is ok. Size is 7,5x5cm
I don't think the tracks can handle 10A current...etc.
Thanks Nelson
Regards
This is my second design, if you find any error please advise me or to make the design better. I will release etch layout later if the design is ok. Size is 7,5x5cm
I don't think the tracks can handle 10A current...etc.
Thanks Nelson
Regards
An externally hosted image should be here but it was not working when we last tested it.
...now you got 3D
An externally hosted image should be here but it was not working when we last tested it.
jacco vermeulen said:
I got tired of Carol, but am thinking to use one of the pictures from Janneman's visit to the lovely women of SEAS. The current av is a solar flare.
The plot which I published depicted the P-channel replaced. I then replaced the N-channel as well and the result is the same -- still peaks at around 500kHz (but I can't do a screenshot with my HP3577.)
I am using 47R gatestoppers.
This is the product of my other labors:
An externally hosted image should be here but it was not working when we last tested it.
Hi Goffe,
Perhaps you could seperate R9 / R10 and move the Q1 and Q2 together (with a "clip")
It wouldn't be difficult to seperate R9 & R10 to fit a bipass cap from V+ to V-, as I have often found this to be beneficial to the sound.
I'd perhaps move the V+ (& V-) terminals(?) to the edge of the pcb, ie, between TH!- Q3 (TH2- Q4) where the round pads are now, and reroute the tracks from R13,21,19 (14, 22, 20) under R11 (12).
Suggest a bit more room around the IN & GND pads, and possibly add a second centre pad for Q5,6 to aid different "pin-outs".
As is often done on NP's designs, adding Cmultipliers to the power rails, near to the main o/p Fets - good results, generally.
Perhaps you could seperate R9 / R10 and move the Q1 and Q2 together (with a "clip")
It wouldn't be difficult to seperate R9 & R10 to fit a bipass cap from V+ to V-, as I have often found this to be beneficial to the sound.
I'd perhaps move the V+ (& V-) terminals(?) to the edge of the pcb, ie, between TH!- Q3 (TH2- Q4) where the round pads are now, and reroute the tracks from R13,21,19 (14, 22, 20) under R11 (12).
Suggest a bit more room around the IN & GND pads, and possibly add a second centre pad for Q5,6 to aid different "pin-outs".
As is often done on NP's designs, adding Cmultipliers to the power rails, near to the main o/p Fets - good results, generally.
I would suggest that people doing F5 pcbs look at Nelson's layout in the pictures of the most recent 6moons article. The location of the "current" feedback resistors are close to the jfet input stage. I believe he is minimizing the trace length on the voltage sensing side of the resistors which are more sensitive to noise than the output stage end of the resistors.