lingDAC - cost effective RBCD multibit DAC design

Elliptic filters are the kind that give the steepest slope of filtering for a given filter complexity (or number of inductors) but they've always been a bit tricky to design, especially for DAC purposes which require unequal termination to get the best utilization of DAC output current. I've until now been content with modifying Chebyshev filters to add stop-band zeroes because this process I understood and Chebyshev filters are simpler to design, especially with unequal terminations. Yesterday though was a milestone - I finally figured out a way to coax https://rf-tools.com/lc-filter/ to help design me an elliptic filter with unequal terminations. If you ask it to create an elliptic filter of any type without the input and output impedances being the same it'll tell you that's not supported. As my filters need to be driven by a current source and terminate in an I/V resistor they can't be designed directly with that tool. But after a lot of tweaking I was able to adjust the values in the equally terminated filter to suit a CCS-driven filter. Here is the frequency response of the result :

Elliptic_5th_FR20221005091918.png


This is a filter intended to be used NOS and has a very useful amount of suppression of the first image frequency (almost 40dB) which is rather good for a design only needing 2 inductors. The price paid is in the passband ripple (about 1dB p-p) and the phase response which is slightly worse than the modified Chebyshev. As I get to understand the tweaking process better I think I'll be able to create lower passband ripple filters.

Elliptic_5th_20221005091918.png

The rather strange termination value is the result of tweaking to get the passband as flat as possible. It is pretty close to what's needed to give a 2VRMS output signal direct from a +/-1mA output DAC which was the intent.
 
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Looks promising...

Regardless the figures and simulations, after you tweaked these filters on paper, it might be wise to test them quickly in terms of sonic results just to see if it materialises in a a new break through, or if spending that much time and effort is not rewarding in that given direction.

No clue on the perceived final sound, just thinking out loud based on all these fabulous efforts you spend and indeed so far this looks like a possible path!

Again well done, good luck and, as ever, let us know what your wife thinks of it ;-)

Claude
 
All quiet here for almost three weeks though I've written a few posts on my blog. I've been working on Stack DAC a bit but more of my time's been spent on a new design using PCM56 which I think deserves its own new thread. Subjectively PCM56 sounds much clearer than a single TDA1387 so I'm using it as a reference against steadily increasing numbers of paralleled 1387s. The question I'm preoccupied with is whether a multibit DAC's SNR is the primary metric to indicate its SQ. If so then paralleling enough TDA1387 will get me to the subjective performance level of the PCM56, all other things being equal.

Since TDA1387 is spec'd at 95dB and PCM56 at 115dB there's a 20dB gap to bridge. Each doubling of the number of chips buys 3dB so in theory we'd need 6-and-a-bit doublings. Somewhere between 64 and 128 paralleled 1387s would get to 115dB SNR. I'm working on a 60 chip stack DAC which I hope to have running in a couple of days, when I've built a second one that'll allow me to go balanced with 120 chips in total. With so much current its easier to build a low noise I/V stage than with a single PCM56 which gives only 1mA peak output. However the low pass filter becomes more and more impractical beyond 120 chips but maybe there's a way to mitigate that by running a higher output level.
 
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I visited Your blog and I like it very much. Please continue :)
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I will start too with some new design for PCM56. Made some day with 56 long time ago and I was very surprised how good the sound it was. I have some pieces left...
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Also thinking about some universal interface for adopting standard I2S from digital interfaces to left justified, separate L and R data simultaneous and stopped clock operation. With option for immersion of MSB to use with TDA1540/41A.
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But I want first finish one day with TDA1387 :)
I read most of the topic. Thanks.
That is the maximum level of power supply for TDA1387?
 

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I visited Your blog and I like it very much. Please continue :)
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Thanks, I plan to post up something about NTD1 I/V stage next.

I will start too with some new design for PCM56. Made some day with 56 long time ago and I was very surprised how good the sound it was. I have some pieces left...
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Yes, I think PCM56 has great potential though I'm a bit concerned about chip variability. I've built a couple of prototypes of DAC with it so far and getting quite a bit of variation in output level. I notice the DS says '+/-30%' variation in output current, which is rather substantial and much more than TDA1387 which has a wide range of +/-14%. So a test jig is looking to be a requirement along with matching.

Also thinking about some universal interface for adopting standard I2S from digital interfaces to left justified, separate L and R data simultaneous and stopped clock operation. With option for immersion of MSB to use with TDA1540/41A.

I've been thinking about doing that too but using an MCU (probably RP2040) rather than logic. Then it can include an upsampler.

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But I want first finish one day with TDA1387 :)
I read most of the topic. Thanks.
That is the maximum level of power supply for TDA1387?

Sorry I can't quite grok your question. Are you asking about TDA1387 power supply voltage?
 
but using an MCU (probably RP2040) rather than logic.
I have been tried CPLD for format "repacked" for TDA1540/41A. working very good. Also Tried some discrete R2R ladder DAC I2S/DSD option with some Xilinx "processor" (don't know now specific type)
Booth nos modes from I2S base.
And third, R2R ladder DAC IC logic ONLY without CPLD
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To be clear - all of the USB-I2S interfaces using some high density cpld/fpga ICs :(
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I think, based on listening tests and measurements, that concentration of HF glitch energy in so small DIE areas, somehow compromising the sound? So I want to give a try with logic ICs from same level of technology (DIP) as DAC chips are?
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In this example I posted, datas are placed in the middle of Latch interval (Fs, LE). It is easy to reconnect the module for PMD100 standard which is more left moved.
It can be used for all formats even up to 32bits and for discrete R2R DAC too, as for serial input data DACs AD series with minor correction.
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Maybe to add Deglitch line? But maybe it will be not a simple...
 
WeChat Image_20221024144845.jpg


60 DAC stack - not yet balanced though - now playing music. Here the I/V stage (top left, on the perfboard) is only resistors to terminate the filter, no active components. The filter (on the red PCB) I'm using here is a spare DecaDAC 7th order one as it has about the right impedance. It doesn't have the same pin connections though hence the blue wires. Two PSUs are needed - one to power the DACs (7.5V, 600mA) and a negative one to provide headroom to the current output of the DACs (-12V, 150mA). Sonic results are very gratifying :)

Next stack of boards currently under construction.

@Zoran - which CPLD do you use and what software to program?
 
The sonic benefits are that the perceived noisefloor drops, the images float more freely in space, instrumental separation improves. There's more punchiness in the bass and generally dynamics get better, everything sounds more natural overall. Those kinds of improvement are what keeps me hunched over my soldering iron for countless hours putting down dozens more DAC chips :D

I don't think its going to be super-costly but I haven't worked out all the BOMs yet. The whole idea of stacking is you can get going for a relatively modest cost - say just one DAC board (12 chips), no filter plus a simple I/V. That will be not much more expensive than Dorati but you do need two PSUs rather than one. Then when you get the urge you can add a filter board and more boards to the stack - with 60 chips its clearly beyond the level of Celibidache in terms of clarity.

Balanced isn't primarily to get a higher output level, its to improve the SNR - and hence dynamics. With two anti-phase signal wires the signal goes up 6dB but the noise only +3dB.

As far as how complicated it is - I'll have a go at explaining design decisions in another post later on.
 
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Many thanks for your kind reply, again!

As of me, I am not interested in balanced as I can't deal with it,, but I must confess I like a lot the modular idea you seem to develop here in order to enhence even further the sound reproduction.

Again, very interesting experiments!!

Have a nice day

Claude
 
Yes TDA1387 max supply voltage, and optimum from Your findings?
Nowadays I go for the maximum long-term safe voltage which is 5.5V to eek the maximum current out. Oh and I also juice pin7 to get even more output current. I guess if you're just making a DAC for yourself, you could go higher than 5.5V, depending on how much you value long-term reliability. I don't know if there is an optimum supply voltage, higher is better in my experience.

@ClaudeG Yes - balanced is very much an acquired taste, I feed the balanced into the trafo of my amp. Trafos don't much care bal vs SE. For the reason of direct connection to the poweramp, I'm working on a volume control within the DAC. The aim there is to eliminate the need for a balanced preamp but still get SNR improvements when not at max volume.

A quick plug for some music - the 60-chip stack is currently rendering this Schubert piano duo recording delightfully :

 
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Pin 7 is Vref. You leave this pin unconnected in Your designs?

Not any longer, I pull it up to VDD with a 100k resistor. This increases the output current.

Do You plan some simple R to GND or some active current network @ Pin7/Vref of TDA1587?
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What kind of Volume control?
.;)

The volume control is still partly at the concept stage. I plan to use a CMOS mux from a resistor string but haven't yet figured out how to get rid of clicks. Probably that'll need some software.
 
Revised (i.e. simplified) Stack boards came in today. We spent some time trying to get the height of the components down below 7mm as that's the spacing determined by the stacking connectors. The TH polymer caps have been swapped for SMD ones - so far these are the only small SMD caps I consider to have decent measurements, they're pretty much the same as the leaded versions. Whereas the normal SMD caps suck really bad (just try measuring their ESR), so we're sticking with leaded ones for where we don't need super-low impedance. They're laid down on their sides.

WeChat Image_20221107221033.jpg
 
I finally got the balanced stacks running a few days ago, so now there's 60+60 chips as source in my setup. Sound is immensely satisfying to listen to but there's an issue I need to address. And that is - heat. The stack of 5 boards still runs a bit too hot for comfort. I'll make some temperature measurements soon but longer-term reliability is a concern here so I'm thinking of options.

First option is turn all boards sideways. This does not look very attractive and is more difficult to mount in a case. Some mechanical re-design would be called for to aid the ability to secure it. With sideways boards, natural convection will take care of cooling provided there are holes in the top and bottom of a case.

Second option - fit a fan. I am sure that only very slow-moving air will be needed but are fans available with speed control that keep them slow and quiet? I plan to do a bit of searching to find out. Since the heat is well distributed rather than a point source the usual CPU cooler solutions aren't really appropriate.

Third option - more radical mechanical re-design to make a chimney rather than a stack.

Fourth option - reduce the chip numbers per board and/or throttle back the overclocking.

What do all you guys think? Any suggestions are more than welcome!