Rd is the "triode" drain resistance, not the output load RL. Rd=μ/gmJ1. See https://www.electronics-notes.com/a...s/triode-valve-vacuum-tube-formula-theory.php
Yes, there is an inconsistancy in the labelling of the MOSFET in the figures and the equations. M1 and M2 refer to the same MOSFET.
Yes, Rk is the resistance of R3+R4
Yes, there is an inconsistancy in the labelling of the MOSFET in the figures and the equations. M1 and M2 refer to the same MOSFET.
Yes, Rk is the resistance of R3+R4
"Rd=μ/gmJ1" clearifies ok.
I'll put it in my simu-box soon.
Smart thing, much likened.
Why this {Vcasc} (#12) ?
I'll put it in my simu-box soon.
Smart thing, much likened.
Why this {Vcasc} (#12) ?
Vcasc defines the quiescent Vds (drain-to-source voltage) operating point for the LU1014D and Vgs for the M2 MOSFET at the desired quiescent operating current.
Granted, but this {(1-k)*Rk} and {k*Rk} [aka R3 & R4] are creating a VgsM2 on their own already, {Vcasc} only lifting VG2 higher then intended!
And what if {Vcasc} is omitted and the lower side of {k*Rk} is connected to S1 (node 'above' {Rs}), the source of J1? (feedback?)
I'd say: simplify - it does not appear in the equations either (obvious, though).
And what if {Vcasc} is omitted and the lower side of {k*Rk} is connected to S1 (node 'above' {Rs}), the source of J1? (feedback?)
I'd say: simplify - it does not appear in the equations either (obvious, though).
This would cause the MosFET gate voltage (G2) to follow the D2 voltage directly (schematic in post #9), very similar to the "pentode" cascode shown in the first post. Adding the Vcasc voltage offsets the G2 voltage, which obviously makes the whole thing behave in a "triodey" way.
I guess @lhquam will have a better explanation.
That offset is required to preserve the "shape" of the triode curves. To obtain a 10X expansion of the Vds range, k must be around 1/10. Consider the "pentode" case, where k=0. Without the Vcasc offset, there would be no idle current.
Be patient, a more complete explanation is underway.
Be patient, a more complete explanation is underway.
#45: Not so, as {(1-k)*Rk} >> {k*Rk}, so only (in the R3-R4 example) 1/9 part of Vd2.
#46: k≠0, and with these {(1-k)*Rk} and {k*Rk} (R3, R4), an offset is already created when {Vcasc} is omitted.
Awaiting further elaboration.
#46: k≠0, and with these {(1-k)*Rk} and {k*Rk} (R3, R4), an offset is already created when {Vcasc} is omitted.
Awaiting further elaboration.
Maybe this will help:
- Start with the Vcasc needed when k=0, the "pentode" condition. Adjust Vg and Vcasc to obtain the desired idle current and Vds[J1].
- Increase k slightly, and readjust Vg and Vcasc to obtain the desired idle current and Vds[J1]. The changes to Vg and Vcasc should be relatively small, roughly proportional to the change in k.
When k=0, {(1-k)*Rk} [::R3] is R3 and {k*Rk} [::R4] is 0 (zero), rendering into a 'pentode' configuration as {Vcasc} prohibit Vd2M2 from changing the G2M2 node. Adjusting Vg (assumed Vg1) and {Vcasc} aka Vg2=Vd1 determines the desired Id (J1) in the ohmic region (ok).
As soon as k ≠ 0, R4 exists and will be part of the equation of (Vd2 -Vcasc) over the R3/R4 divider. And yes, in some respect proportional to the k factor indeed. But as k cannot be 0 for this application, Vcasc has become superfluous instantaneously.
I do follow your thoughts, I do admit the viability of this configuration. Actually, it is great! But Vcasc is a mindtrap.
As soon as k ≠ 0, R4 exists and will be part of the equation of (Vd2 -Vcasc) over the R3/R4 divider. And yes, in some respect proportional to the k factor indeed. But as k cannot be 0 for this application, Vcasc has become superfluous instantaneously.
I do follow your thoughts, I do admit the viability of this configuration. Actually, it is great! But Vcasc is a mindtrap.
Are you suggesting totally discontinuous behavior when k becomes just slightly non-zero?
I suggest you try some simulations of the circuit.
Perhaps this image will help explain Vcasc.
The left schematic shows a fragment of the F3 (or Zen9) modulated cascode which has a voltage divider between M2D and ground with a large capacitor across the lower resistor.
In the remaining schematics the cascode is modulated by a fraction of the AC voltage of the drain of MOSFET M2,
with the 4th schematic being that of post#1.
In all variations, the quiescent (idle state) voltage at M2G is the same, maintaining the same operating point (bias current and LU1014 Vds).
The left schematic shows a fragment of the F3 (or Zen9) modulated cascode which has a voltage divider between M2D and ground with a large capacitor across the lower resistor.
In the remaining schematics the cascode is modulated by a fraction of the AC voltage of the drain of MOSFET M2,
with the 4th schematic being that of post#1.
In all variations, the quiescent (idle state) voltage at M2G is the same, maintaining the same operating point (bias current and LU1014 Vds).
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Don't destroy theory by data.
Don't worry. I built the modulated cascode circuit as described and gave it to my curve tracer. Once the magic smoke was out, and new parts were in, the curves looked as in the attachment. Pretty cool!
Did I just build a holy grail?
Don't worry. I built the modulated cascode circuit as described and gave it to my curve tracer. Once the magic smoke was out, and new parts were in, the curves looked as in the attachment. Pretty cool!
Did I just build a holy grail?
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Poor man's SIT, with an easier gate to drive. 
..... if you can keep the oscillation under control.
I'll be making this modification to my amplifier when I get some time.
..... if you can keep the oscillation under control.
I'll be making this modification to my amplifier when I get some time.
See measured curves in the attachment. There is something funny going on a low voltages, and the curves are compressing at high voltages.
Well, the LU is a SIT, but it's cheap and abundant. I am not concerned about oscillation, since my build is a rat's nest with looong wires and looooops. It seems to behave ok.Poor man's SIT, with an easier gate to drive.
..... if you can keep the oscillation under control.
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I am not sure what you mean by "clipping in" and "full circuit". Can you explain?