good morning and thank you very much for the links
I'm no expert but your requirements look similar to those of a headphone amplifier. I would look at circuits designed for them.
Compared to line stages, they usually have higher undistorted Voltage outputs and are capable of driving even more difficult loads.
I would also look at amplifiers known for having good headphone outputs.
I'm no expert but your requirements look similar to those of a headphone amplifier. I would look at circuits designed for them.
Compared to line stages, they usually have higher undistorted Voltage outputs and are capable of driving even more difficult loads.
I would also look at amplifiers known for having good headphone outputs.
Actually better not. Where did you read this?
The main requirement remains the line level (and loads >10KOhm).
Would this explain the fact that T4 Collector's DC operation point is set at 19.36V (only 1.6V below 21V rail) and yet it can output AC voltages up to 7Vpp with relatively low distortion?
If gain is 1 it seems that setting T4 collector at ca. 11V will destroy the THD and it will also have early chocking (either high or low). Instead setting this DC at either high (19V) or low (ca 4V) will improve both THD and chocking levels.
If gain is mid high (up to 50dB) : the T4 collector DC point seems to like staying at PS midrange (11V), for both optimal THD and large excursions.
If gain is maximum (something around 60-70dB): the DC point asks again to be set NOT in the middle.
So many questions about it. I think this circuit is a far cry from "textbook level" as it was described by others. Or maybe I do not know which textbook has a full chapter on it 🤔
Any further help to understand it will be greatly appreciated!
and, which transistor sets the Gain actually: the T2 (error amplifier) or the T4?
It seems to be T2...
It seems to be T2...
please, care to post the equivalent CFP (standard one with NPN+PNP) of comparable quality, which has also a virtual ground input?
This is an example of CFP using sensible values, shown with a 6V peak drive:
The (simulated) THD is ~19ppm, which is not bad. Actual figure will probably be somewhat higher, but it is a reasonable indication.
The (simulated) THD is ~19ppm, which is not bad. Actual figure will probably be somewhat higher, but it is a reasonable indication.
The full N version should perform similarly, but probably a smidgeon better if the values are optimized: the use of capacitors allows a "cheat", because the DC and AC requirements are decoupled, offering the best of both worlds. That's the way tube amplifiers perform. However, each coin also has a flip side, in this case additional parasitic poles and possible stability and headroom issues.
You should simulate the frequency response of your N CFP, it could reveal some issues.
The same kind of trick could be used in this complementary CFP, by adding a voltage translator between the collector of Q1 and the base of Q2 and using a larger load collector resistor for Q1 .
The translator could be a bypassed stack of forward biased diodes, or a low voltage zener.
However, I am not going to even simulate it, because the gains will be marginal, and this kind of topology brings additional constraints on the headroom, bias, etc., as you have noticed in your circuit.
The plain-vanilla CFP has the normal limitations of any SE stage, but very little more. As soon as you try to cheat on one aspect, you degrade most of the others. Of course, engineering is a matter of trade-offs, and if you want the absolute best performances within your specs enveloppe, it can be done but in this case I don't think it is worth the trouble
You should simulate the frequency response of your N CFP, it could reveal some issues.
The same kind of trick could be used in this complementary CFP, by adding a voltage translator between the collector of Q1 and the base of Q2 and using a larger load collector resistor for Q1 .
The translator could be a bypassed stack of forward biased diodes, or a low voltage zener.
However, I am not going to even simulate it, because the gains will be marginal, and this kind of topology brings additional constraints on the headroom, bias, etc., as you have noticed in your circuit.
The plain-vanilla CFP has the normal limitations of any SE stage, but very little more. As soon as you try to cheat on one aspect, you degrade most of the others. Of course, engineering is a matter of trade-offs, and if you want the absolute best performances within your specs enveloppe, it can be done but in this case I don't think it is worth the trouble
Replace R1 with a current source (that works well at 0.6 V) and you don't throw away loop gain anymore and you get rid of the nonlinear current division between R1 and Q2. Then replace Q2 with a BC557C and you again get more loop gain.
Very compelling and I will try to build it.
A few important questions pops in my mind: same is the situation regarding performance for using CFP in amplifier configuration, i.e. for EQ purposes (to replace completely the Revox solution)?
Or we see limitations in the standard CFP side vs the using the tricks for 2xNPN?
Will such use of standard CFP for EQ purposes be possible with same performances (as Revox) only for mid-high gain, or it can do EQ also for a line level buffer setup?
A few important questions pops in my mind: same is the situation regarding performance for using CFP in amplifier configuration, i.e. for EQ purposes (to replace completely the Revox solution)?
Or we see limitations in the standard CFP side vs the using the tricks for 2xNPN?
Will such use of standard CFP for EQ purposes be possible with same performances (as Revox) only for mid-high gain, or it can do EQ also for a line level buffer setup?
Indeed, but what is the worst evil: a RC circuit or a transistor? Anyway, I made a point of keeping things as simple and minimal as possible, including the C selection (which might be better), but Hfe is correlated to Vaf, meaning that an increased gain will not generally translate into an equivalent improvement in linearity performance.
Marginal gains are certainly possible without additional components, but a physical optimization will probably be required
Marginal gains are certainly possible without additional components, but a physical optimization will probably be required
With silicon, the P transistors tend to have a lower Vaf, meaning degraded linearity, but this is very marginal, and P types have other strong points, like a lower Rbb and consequent noise.
However, the additional resistors required with the capacitor-coupled N version are probably going to negate this small advantage.
Any proper unity gain stage should perform equally well in all situations.
I don't know the exact context, why Revox decided to use a relatively complex and unpractical solution, but they probably had rational reasons
thanks to both!
solid state wise I am familiar with the details.
topology wise (electronics) it will take me a while until I assimilate all this info. Until not long ago I was fooling around exclusively with opamps (mostly as hobby). I switched to 'more advanced' discrete circuits only one year ago.
Above 1GHz the saying goes like this: 1$ antenna values as much as 10$ HW (matching and amplification).
For audio frequencies, it is probably the opposite? I should put in 30€ in HW for a 300€ tape head?
And 30€ HW is probably not meaning a simple circuit.
solid state wise I am familiar with the details.
topology wise (electronics) it will take me a while until I assimilate all this info. Until not long ago I was fooling around exclusively with opamps (mostly as hobby). I switched to 'more advanced' discrete circuits only one year ago.
well, I guess this depends 🙂
Above 1GHz the saying goes like this: 1$ antenna values as much as 10$ HW (matching and amplification).
For audio frequencies, it is probably the opposite? I should put in 30€ in HW for a 300€ tape head?
And 30€ HW is probably not meaning a simple circuit.
I know that I am spending too much time with the simulator. Instead, I should use this time to learn to compute myself (by hand) any circuit.
But, is it my fault that most books (and Youtube now) give the walk-through only for basic CB, CE and CC topologies? The jump from them to advanced circuits is too big for me to do it alone.
Just today, I found an interesting article from 2023 proposing a new Sziklai variant (with emmitters connected: https://www.researchgate.net/profil...WQiLCJwcmV2aW91c1BhZ2UiOiJwdWJsaWNhdGlvbiJ9fQ).
It took them exactly 70 years to see this better variant. So, these things are not simple to compute (even in the time of Spice simulators), I guess.
But, is it my fault that most books (and Youtube now) give the walk-through only for basic CB, CE and CC topologies? The jump from them to advanced circuits is too big for me to do it alone.
Just today, I found an interesting article from 2023 proposing a new Sziklai variant (with emmitters connected: https://www.researchgate.net/profil...WQiLCJwcmV2aW91c1BhZ2UiOiJwdWJsaWNhdGlvbiJ9fQ).
It took them exactly 70 years to see this better variant. So, these things are not simple to compute (even in the time of Spice simulators), I guess.
you should ask middle aged audio designers who had to do just this in the past I imagine they cry just at the memory... it must have been a nightmare
This circuit cannot possibly work: it looks like an AI-generated article and diagram.
If the PNP is turned upside down, it becomes a repeater circuit, which has limited applications
So, then it has to be "better" 🙂
In my hands, simulations of proposal using published parameters did not work. Thanks LV for confirmation and explanation.
Fooling around with parameters, somehow it did work, but not equal or better than original Sziklai.
I am slowly progressing here. What do you mean, the error between which currents, or which nodes? How does works this error amplifier? What should be zeroed?
In so far I see, AC current T4 = current R4 + current (R3+R6) + current C4+P1
but the driving of Current T4 is set by base current T2 alone, where I see only one input (not a "input+error" what you suggest).
Clearly I am missing something or understand it wrong.
It may not be obvious, but a transistor is a differential (transconductance) amplifier, albeit a very asymmetrical one: it looks at the difference between its emitter and base voltages, and if there is any, it converts it into a non-zero collector current.
Thus, when the input voltage and the feedback divider voltage aren't perfectly equal, T2 sends a signal to T4 in order to achieve (near-perfect) equality
Thus, when the input voltage and the feedback divider voltage aren't perfectly equal, T2 sends a signal to T4 in order to achieve (near-perfect) equality
Thanks!
Very difficult to see this picture when the Vbe is floating. I guess that solving the equations or the experience probably helps a lot. Really not much to find in internet or EE books about such problems in details without the correct keywords.
So, are you talking about how the input current (line or play head) is driving Q2 - in clear unbalance ref to emmitter, or about the eventual errors due to Q4 and other circuit effects showing on Q2 emmitter in clear unbalance ref to Q2 base? Or both (probably)?
How do we know there is no oscillation or bad close loop effect on noise, THD etc?
I mean, probably, to ask, how do we think 'proper bias' here?
Very difficult to see this picture when the Vbe is floating. I guess that solving the equations or the experience probably helps a lot. Really not much to find in internet or EE books about such problems in details without the correct keywords.
So, are you talking about how the input current (line or play head) is driving Q2 - in clear unbalance ref to emmitter, or about the eventual errors due to Q4 and other circuit effects showing on Q2 emmitter in clear unbalance ref to Q2 base? Or both (probably)?
How do we know there is no oscillation or bad close loop effect on noise, THD etc?
I mean, probably, to ask, how do we think 'proper bias' here?