Phase noise in DS dacs

Interesting read.

As we all know, exp(jwt) is cos(wt)+j sin(wt) which is a complex number running in a circle.

A dac can play complex signals if you put real on left channel and imaginary on right channel. It's just a sin and a cos.

Acquire both channels with ADC (soundcard), and you get the original complex number back.

Multiply with exp(-jwt) and extract modulus and angle

angle gives phase shift between dac clock and adc clock, so you get a time domain view of jitter. No FFT!
 
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Acquire both channels with ADC (soundcard), and you get the original complex number back.

Multiply with exp(-jwt) and extract modulus and angle

angle gives phase shift between dac clock and adc clock, so you get a time domain view of jitter. No FFT!

I like where this is going.

This post and the whole thread are relevant. With four Channels you can make much more precise or deep measurements when it comes to close-in Phase Noise. The processing isn't totally complete, but I know what the Big Boys do with their multi-thousand $$ gear, which I'll probably never buy. The post and the graphs show the calculations with simulated data but using four Channels for the processing.

The hardware needs are quite specific. I have two such Quad-Channel ADC cards. I can provide one to someone who'd like to do a DIY build. This can be paired either with an FPGA or the computer for processing.
 
By the way, referring to earlier posts here, I see the microphony of caps. This is well known.

However, has anyone thought of checking the effects of vibration on the crystal or clock itself? That would be an interesting area of exploration because I believe the crystal itself can behave differently under vibration - there should be an incidence on CIPN and hence on SQ.

However, before worrying about all this, there's a lot of phenomena whose effects can totally mask those of CIPN.
 
...so you get a time domain view of jitter.
Not quite clear to me. Playback and recording from the same clock tends to be jitter canceling. You send out a sequence of samples. Say, they get played back and re-recorded at the same wrong time. You get back a sequence of samples. The assumption is that the sequence is evenly spaced in time. Any errors in sample values are presumed to be amplitude errors, maybe added noise and or nonlinearity in the converters. Am I missing something?
 
Not quite clear to me. Playback and recording from the same clock tends to be jitter canceling. You send out a sequence of samples. Say, they get played back and re-recorded at the same wrong time. You get back a sequence of samples. The assumption is that the sequence is evenly spaced in time. Any errors in sample values are presumed to be amplitude errors, maybe added noise and or nonlinearity in the converters. Am I missing something?
True!
Unless you send the sound card spdif output to a wm8805 based dac and you want to know how much jitter the chip adds. In this case having the spdif transmitter and the adc use the same clock is an advantage...
 
Interesting read.

As we all know, exp(jwt) is cos(wt)+j sin(wt) which is a complex number running in a circle.

A dac can play complex signals if you put real on left channel and imaginary on right channel. It's just a sin and a cos.

Acquire both channels with ADC (soundcard), and you get the original complex number back.

Multiply with exp(-jwt) and extract modulus and angle

angle gives phase shift between dac clock and adc clock, so you get a time domain view of jitter. No FFT!
If you haven't got two channels at your disposal, you can also use one channel and filter off the sum product, like radio engineers have done for more than a century:

cos(omega t) = 1/2 exp(j omega t) + 1/2 exp(-j omega t)

Multiply by exp(-j omega t) and you get 1/2 + 1/2 exp(-2 j omega t).

Now all you have to do is filter and multiply by 2.

With either method, when the clocks are independent, you are bound to get a slope in the phase due to frequency differences.
 
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Are you referring to a 'Three Corner Hat' phase noise measurement?
It's been a while since I touched the processing code, but that would be the method used to derive the first graph.

There's another thing (state-of-the-art) I did which the best R & S and some others do and that's in the second graph and uses 4 Channels.

John, who wrote R.E.W., could easily adapt it to do the same thing IMO.
 
Multiply by exp(-j omega t) and you get 1/2 + 1/2 exp(-2 j omega t).

Now all you have to do is filter and multiply by 2.
Yup. "software detector". That's how the "output stage shootout" works. Note if the frequency is such the period is an integer number of samples, you dont need to filter, only average over a period... because then exp(2jwt) averages to zero over the period... If it's not an integer number of samples it's more annoying.
 
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Hehe, thanks.

When I say measurements are important, I don't mean that as direct predictable influence on how it will sound (although there's definitely a correlation).

What I mean is, if the circuit is supposed to do a thing, then there should be a measurement that shows how well it does the thing, so that it can be optimized to do the thing. The measurement that will work best for that is not necessarily one of the "industry standard" ones.

For example, since we're in this topic, I had a WM8805 and I noticed the subbu guys were spending months swapping capacitors and whatnot trying to make it sound better. ES9023 is supposed to remove jitter, but according to them, the WM8805 did "something" that the ES9023 did not remove, since tweaking the WM8805 did something to the sound. I assumed they were not crazy. Therefore:

I used one board with a USB2 micro and a WM8805 to output SPDIF, clocked by its own local canned oscillator. That WM8805 acted as master, so it generated LRCK, BCLK, slaving the micro that output the I2S.

Then I connected that SPDIF output to the input of another WM8805.

The job of that WM8805 was to read the SPDIF and extract the clock from it.

So I measured how well it did what it was supposed to do, by comparing the master clock from the SPDIF transmitter, with the recovered SPDIF clock of the SPDIF receiver. Using high-tech equipment known as "XOR gate" and a lowpass filter, it will output the phase shift between these two square waves as DC that will wobble according to the varying phase shift (ie, jitter) between these two. One can also look at the two square waves on the scope, while triggering on one.

Another simple measurement is to just feed the 44.1k wordclock into a soundcard capable of sampling at 192k and doing a FFT. That will give you phase noise on the wordclock, without phase noise from the DAC, so it has a lower noise floor. It requires tuning the soundcard for low jitter. By using a software detector, phase can be plotted directly across time, so what the oscillators do becomes quite visible. If LRCK from the SPDIF source and the SPDIF receiver are acquired on two separate channels at the same time, soundcard jitter can be removed.

Then I tried a 74HC divider to make a pseudo-wordclock from the MCLK and checked that with the soundcard, that's how I found out WM8805 generates different kinds of jitter on MCLK and LRCK... They should be synchronous, but they're not! lol

So that's how I found out there was no way to make the WM8805 crystal oscillator behave. No matter where I put the crystal, how I shielded it, it was always full of trash. But when the receiving WM8805 was fed from a canned XO instead of using a crystal, its output became squeaky clean.

So the result was a 50c tweak: one flop to divide the clean 50MHz ES9023 clock into 25MHz, which WM8805 accepts.

I did not do a listening test on that one.
You must have had a special Subbu DAC as we never used WM8805.
 
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Yes that's where it all starts :D

BTW I still regret not having used the (already bought) canned XO's for the WM8804. It was the intention to implement those but I could not find space for it including a separate regulator. As a kind of curse they tend to show up always when I don't need them.
 
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