Transfer gates. Not that good at really high speed.
There are better options. Ask MvG.
Thor
One of my DIY projects unintendedly produced clearly non-Gaussian noise. It was a microphone preamplifier consisting of a degenerated differential pair with split tail current source and a transimpedance amplifier. At low gain settings, the tail current source dominated the noise, and I had made that with a CA3046 that had popcorn noise.
It sounded like a rotten contact and on an oscilloscope, you could see the voltage jump up and down randomly between two values. The probability distribution must therefore have been bimodal.
If there would have been 100 crystal defects or whatever it was producing such jumps independently, the result would have been approximately Gaussian, but apparently there was only one random thing generating these jumps. Hence my remark about adding a limited number (in this case only one) of random variables.
If this is a reply to the test I linked to, I don't see the relation. My test was meant to check whether higher than second moments have an effect on the sound of noise and whether dithering such that those moments become independent of the signal is of any use. The answer to the first question appears to be yes and the answer to the second no, but because of a mistake of mine, the results were not entirely conclusive.
The first question is directly related to possible audible differences between noise processes with the same power spectral density but different probability distributions. Mooly and PMA certainly had the impression they heard differences and had ABX test results that confirmed that, but I failed to check if they could also hear a difference between two realizations of the same random process.
Long story short, I agree with your assertion that noise processes with the same power spectral density but different probability distributions may sound different.
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What is most funny, that you can use such inductors with hysteresis distortion just fine, if you make an output stage and filter where there is no net audio signal in the inductor, open loop and get low distortion anyway.
All it takes is design according to RF/SMPS principles and not Class AB amplifier ideas bodged onto Class D.
BTW, I'm not even sure it's core hysteresis (unless the core is chosen very poorly). Self oscillating amplifiers switch at much lower frequencies than at idle. Usual (cone) dome Tweeters have a lot of eddy current distortion that with a lot of carrier breakthrough can cause a lot of "transient" distortion that is hard to measure but easy to hear.
Thor
Here is Bruno's story on the hysteresis distortion thing:
https://purifi-audio.com/blog/tech-notes-1/this-thing-we-have-about-hysteresis-distortion-3
IIRC Lars Risbo aka @lrisbo said something about hearing a similar effect in speakers.
https://purifi-audio.com/blog/tech-notes-1/this-thing-we-have-about-hysteresis-distortion-3
IIRC Lars Risbo aka @lrisbo said something about hearing a similar effect in speakers.
Is he serious? In magnetics for SMPS all he writes about is well defined.
Any tube amplifier has hysteresis in the output transformer. As has any Microphone transformer.
How come it only causes problems in the output of a Class D Amplifier?
https://purifi-audio.com/blog/tech-notes-1/this-thing-we-have-about-hysteresis-distortion-3
I suspect it is ALWAYS a speaker interaction effect.
The problem is absent with planar tweeters, IME, but very strong with low inductance dome tweeters.
Thor
Talking of listening to satellite radio...
https://hifihaven.org/index.php?thr...iend-from-diyaudio-and-his-gifts-to-me.11515/
https://hifihaven.org/index.php?thr...iend-from-diyaudio-and-his-gifts-to-me.11515/
Maybe its like some problems with DSD, the step-size is large? Otherwise, maybe it has to to do with ferrite versus iron (particularly thin soft-steel laminations with a lot of nickel in it)?
You were the guy who suggested there was something there, such as a large common mode ripple and a cure to solve this by using a second Dac to interleave, but so far no proof.
You brought forward the point of CM corruption in the digital stage, the analogue stage is a not taking part of that, it's a different issue.
I was simulation out of curiosity with a complete open mind to find out whether you were on to something.
Apart from randomly distributed rise and fall times in the shiftregister flip-flops that may cause glitches in the sub nsec, I don't see anything else that may cause trouble as long as the set up time and hold times are met, under the condition that the PCB is properly constructed to prevent crosstalk and reflections from improper terminations, which I'm sure Marcel did properly.
I may have overlooked something, so please come with some evidence, or else we can close the CM discussion.
Hans
This was the room?
If so, I already know it was problematic. Having an untreated room with many pairs of speakers in it is already a serious error for proper listening tests. Try removing all unused speakers and all musical instruments from a room, then treating the room, and then do the serious listening. Otherwise there are all sorts of interactions, reflections, absorbers, passive radiators, etc., affecting the sound. Just a word of warning for the unwary. BTW, Benchmark made this same error which they showed a pic on their website of their listening room with multiple sets of speakers.
Well, I have prototyped class D Amplifiers that are not "Eigentakt" but rigidly synchronised and use a multiple phases in parallel that switch in quadrature for a very high effective switching frequency and have no carrier breakthrough that degrades wideband SNR measurements, or indeed hysteresis distortion.
IF you ask me, the real problem of most class D Amplifiers is a low switching frequency, combined with "self-oscillation" that makes the switching frequency variable and dropping with output power, combined with a filter that doesn't really filter that much at high output.
In my prototype each individual amplifier switches at 32FS ( I also designed a commerical product with a 32FS clock locked Class D Amplifier), but using four in quadrature gives an effective 128 FS switching frequency for four amplifiers. So yes, that's a DSD128 Power Amp. With a Multiphase DC-DC convertor synchronised to the same switching frequency master and stepping up from 12V DC to as much as 48V dynamically (in some ways a tracking class D Amplifier if you so want).
I wish someone would offer me the cash to develop this into a wholly digital system that can be turned into a Chip, and a reasonable revenue share from sales. There is a lot of potential.
At the output of the amplifier to speakers the carrier breakthrough is > 100dB down on the signal, with a filter that is both simple, very few parts and allows > 100khz audio bandwidth. HD and other nonlinearities are amenable to classic error correction using a small class A Amplifier.
Having effective 6MHz switching from four phases cut's the switching ripple so much to start with, a very small amp is fine.
The whole circuit could be integrated as a chip with multiphase boost convertor and multiphase output, all at effective ~6MHz running from 12V with 48V peak rails and ~30V RMS maximum out.
Mind you, not 30V RMS according to FTC, but that's not needed for Music. Even Oasis "Morning Glory" has 8dB crest factor, so we need (say) > 100W peaks with 20W average output power.
All with I2S in and on board DSP for EQ, dynamics and etc. I think with recent processes used in DC-DC chips 8 Channels @ 64FS (DSD) are possible and a HQ 2-Channel mode with 4 Channels "interleaved" for effective 2 channels at 256FS.
PCM/DSD in in direct to voice coil all digital with an aux DAC (which is where a FIR DAC may come in) and class A (A/B?) error correction Amp on chip.
Any takes to drop a few millions? Sony? Probably not.
Thor
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Indeed.
No. Not at all.
I suggested that observed rises in HF HD may be down to the interaction of analogue stage (likely needing better sim's and models than LTS allows) with the know common mode issue in RTZ DAC's.
I certainly see "spikey" stuff in your sim, but DM. In this case interleaving would mitigate, but much less than with CM. But your SIM is first of all far from complete (making it with all due respect of questionable value) and it lacks a rigorous demonstration (including to oneself, out of curiosity) of the problem and how MvG's DAC solves it (or not).
Let me offer you a question.
IF you simulate real IC's, what is the holdup capacitance on outputs and what is the pull down/up resistance? At the speeds of your sim, could this cause an unloaded FIR DAC to show a 1/2 VCC common mode, that might not give the same result if the output is loaded?
Again, what is your question that you try to answer by experiment and have you verified your method is suitable? It used to be called the scientific method.
And maybe I am wrong and the problem is not actually CM but DM. MvG's complete circuit cannot tell the difference between DM and CM carrier breakthrough until the CM servo get's involved.
I remember already closing it and stating that I had lost the argument.
Thor
Regarding the output stage, IMHO the sound is coming out at the end is not as good as the dac board itself is capable of producing. Thor hasn't heard the dac, but apparently he has some experience with similar although maybe not exactly the same dac circuits where noise problems were found to affect the output stage processing. I will agree with Thor on this: there is almost certainly some problem going on between the dac and the output stage, and to me its quite audible. Why just to me? Maybe its that I am used to better, or maybe something else. I believe I already got better from Marcel's dac when I didn't use the output stage board. Therefore the question arises as to whether anyone else believes there could be a problem and or if anyone cares to investigate further. I would also agree with Thor that scope measurements are probably indicated using on a physical dac and with a fast 4-channel scope (maybe one with active probes). Or, I maybe I will just try a whole different approach with Marcel's dac board at some point. But I already said if that's the path, then what I can share about the findings will probably be limited.
By saying the above, by no means is it my intention to be critical of Marcel or of anyone else. Would just like to know if we can get it together to make any progress on this for sake of the betterment of diy dac building, or if we are going to let it drop because of disagreement and or lack of interest in doing the investigational work that is probably indicated. Be nice if someone with a Marcel dac would loan it to Thor to take a look at. I already looked at one and formed some direct opinions about it. That said, I do have a 600Mhz, 4-channel scope, but only one active probe, and not enough hands to hold 4-probes with spring grounds while adjusting the scope. It means the dac would have to be modified in some way for attaching low ground inductance probes.
By saying the above, by no means is it my intention to be critical of Marcel or of anyone else. Would just like to know if we can get it together to make any progress on this for sake of the betterment of diy dac building, or if we are going to let it drop because of disagreement and or lack of interest in doing the investigational work that is probably indicated. Be nice if someone with a Marcel dac would loan it to Thor to take a look at. I already looked at one and formed some direct opinions about it. That said, I do have a 600Mhz, 4-channel scope, but only one active probe, and not enough hands to hold 4-probes with spring grounds while adjusting the scope. It means the dac would have to be modified in some way for attaching low ground inductance probes.
I wish you good luck with your scientific method to solve a problem that yet has to be defined.
Hans
What problem? You and bohrok tell me there is no problem and I already agreed with you and him.
All DAC's without large on chip FIR or other filters (which is many) have these issues.
1:10 probes should do. Solder wires to the PCB, a "shelf" with a curve to rest the sleeve on and a hook to rest the pin in, some blue tack. Not pretty, but we are not running a Miss Thailand beauty contest.
Thor
Okay. But I don't have a Marcel dac here anymore. It was returned to its owner, Acko.
BTW, last time I installed some u.fl connectors onto the board to access signal lines. I have adapters from u.fl to probes. Probably more capacitance that way, but wasn't looking for glitches at the time.
Mark,
Maybe these images can help for further investigations.
The reconstruction's filter output was measured in diff mode while feeding the the Firdac with 0101010 or 55h, generated by Marcel as DSF files for various DSD rates without having applied noise shaping.
This pattern should give a constant output from the Firdac shiftregisters and should ideally result in a flat noise spectrum from the reconstruction filter in the audio band.
The same test was done with a silent track, noise shaped during the conversion from PCM to DSF giving an idle tone of 01101001 or 69h with added noise.
Now the content of the shiftregisters is varying and so is the output, but after filtering the diff mode signal should still be the same as with 55h since the average between both patterns is still the same.
Now the following attachments are shown.
1) The noise spectrum of my measuring chain when terminating the input with the same 2*50R resistors as the output of the reconstruction filter.
Noise spectrum is flat without peaks at -167.1dBV.
2) Then the noise was measured from the reconstruction filter alone with the 8n2 caps shortened at -151.6dBV.
3) Next is the spectrum shown while playing a silent track through Marcel's Solid State Dac, just as a reference to the RTZ Firdac.
Spectrum is still very nice and flat at -148.8dBV without any peaks.
4) Output from the RTZ Firdac for DSD 256 while showing in one image both the 55h in blue and the 69h pattern in purple.
The purple spectrum for the silent track is 6dB above the 55h spectrum with resp -144,4 and -150.7dBV.
Since the filter alone is already at -151.6dBV, the 55h spectrum is in fact a number of dB's lower in level, but the point is that both spectra are far from clean for which I don't have an explanation.
For the 55h pattern no noise shaping was done, so that can't be the cause.
It could be the Amanero producing these spikes or the RTZ Firdac.
The other thing that strikes is that in both spectra the large peaks are at exactly the same frequencies.
5) The same as in 4) but now for DSD512.
The blue spectrum is still at exactly the same level of -150.7dBV, but the purple silent track level is quite a bit higher at -136.5dBV.
Since both blue spectra are still at the same level, I suspect again the Amanero for worsening the 69h pattern level that much.
But the point is that again both spectra are far from clean, and closer inspection learns that the spectral lines are roughly 150Hz apart.
Looking again at the DSD256 spectrum, the spectral lines are ca.75Hz apart and for DSD128 even 37.5Hz.
So, the reason for showing 1)to 3) was to be certain that the spectral peaks in 4) and 5) are from the DSD circuitry and not from my measuring gear.
And since the spectral peaks are equidistant an directly related to the DSD rate it cannot be caused by mains interference IMO.
But at least RTZ Firdac plus Amanero sounded less to me as the Solid State Dac, which seems to make sense when looking at these spectra.
To exclude that all these anomalies are not caused by the RTZ Firdac, a better converter as the Amanero will have to be used.
Hans
Maybe these images can help for further investigations.
The reconstruction's filter output was measured in diff mode while feeding the the Firdac with 0101010 or 55h, generated by Marcel as DSF files for various DSD rates without having applied noise shaping.
This pattern should give a constant output from the Firdac shiftregisters and should ideally result in a flat noise spectrum from the reconstruction filter in the audio band.
The same test was done with a silent track, noise shaped during the conversion from PCM to DSF giving an idle tone of 01101001 or 69h with added noise.
Now the content of the shiftregisters is varying and so is the output, but after filtering the diff mode signal should still be the same as with 55h since the average between both patterns is still the same.
Now the following attachments are shown.
1) The noise spectrum of my measuring chain when terminating the input with the same 2*50R resistors as the output of the reconstruction filter.
Noise spectrum is flat without peaks at -167.1dBV.
2) Then the noise was measured from the reconstruction filter alone with the 8n2 caps shortened at -151.6dBV.
3) Next is the spectrum shown while playing a silent track through Marcel's Solid State Dac, just as a reference to the RTZ Firdac.
Spectrum is still very nice and flat at -148.8dBV without any peaks.
4) Output from the RTZ Firdac for DSD 256 while showing in one image both the 55h in blue and the 69h pattern in purple.
The purple spectrum for the silent track is 6dB above the 55h spectrum with resp -144,4 and -150.7dBV.
Since the filter alone is already at -151.6dBV, the 55h spectrum is in fact a number of dB's lower in level, but the point is that both spectra are far from clean for which I don't have an explanation.
For the 55h pattern no noise shaping was done, so that can't be the cause.
It could be the Amanero producing these spikes or the RTZ Firdac.
The other thing that strikes is that in both spectra the large peaks are at exactly the same frequencies.
5) The same as in 4) but now for DSD512.
The blue spectrum is still at exactly the same level of -150.7dBV, but the purple silent track level is quite a bit higher at -136.5dBV.
Since both blue spectra are still at the same level, I suspect again the Amanero for worsening the 69h pattern level that much.
But the point is that again both spectra are far from clean, and closer inspection learns that the spectral lines are roughly 150Hz apart.
Looking again at the DSD256 spectrum, the spectral lines are ca.75Hz apart and for DSD128 even 37.5Hz.
So, the reason for showing 1)to 3) was to be certain that the spectral peaks in 4) and 5) are from the DSD circuitry and not from my measuring gear.
And since the spectral peaks are equidistant an directly related to the DSD rate it cannot be caused by mains interference IMO.
But at least RTZ Firdac plus Amanero sounded less to me as the Solid State Dac, which seems to make sense when looking at these spectra.
To exclude that all these anomalies are not caused by the RTZ Firdac, a better converter as the Amanero will have to be used.
Hans
Attachments
Hans,
Thank you for the information. Already did have a pretty good idea about the Amanero and few other issues external to the dac itself. If and when I end up with a dac here I will see that those things are attended to first. Maybe I will build a dac, but not an output stage. Will have to see.
Mark
Thank you for the information. Already did have a pretty good idea about the Amanero and few other issues external to the dac itself. If and when I end up with a dac here I will see that those things are attended to first. Maybe I will build a dac, but not an output stage. Will have to see.
Mark
????
"Using Amanero" in your case means:
Amanero local clocks are used? Or do you have local clocks that are used in the first reclocker of MvG's DAC, reclock BCK and then drive MvG's DAC?
The clocks on Amenero are not that clean. Actually the BCK from all the USB -> I2S is not very clean.
Marcel's original design needs a super clean BCK, the clock doubler will add jitter (in part because it cannot have 50% Duty
All my USB audio products use NC7 popcorn logic Flip Flop's to re-clock BCK & Data, from the local Crystal or DLL Clock synthesiser.
A lot of the clock problems with these converters appears to be sloppy programming. Edges are not aligned and while all FPGA's and devices like XMOS allow the outputs to be driven by latches clocked from MCK, it is usually not done.
Past that, what you see with DSD256 vs DSD512 as noise rise I have observed with both integrated circuit and "discrete" DAC's (not always at DSD512, but at DSD2048 it gets dicey very rapidly. DSD1024 is also pushing it in terms of SNR).
My interpretation has always been that we are now at points where the logic update speed is so fast, issues from lead frame and bond wire impedance no longer decay to steady state before the next clock edge. If not sending an absolute steady state pattern (e.g. 0xAAh or 0x55h) that allows the system to "settle" to a degree.
As RTZ adds extra transitions it would be more sensitive to this problem than NRZ. A workaround is to lower the switching frequency and use multiple DAC's in Quadrature, I think it needs a FPGA to create the relevant data streams. I cannot think of a way that uses simple logic. Running (for example) four FIR DAC's at DSD512 interleaved gives an effective DSD2048 sample rate.
Switching (for example) to much physically smaller QFP IC's (from TSSOP) in discrete DAC's reduced the problem. Logic families are also an issue.
Ideally we want super fast logic in QFP etc cases for all the control logic, but that means 1.8V logic.
For the actual DAC part ideally we would run from +/- 15V with a "center" position for RTZ and either +15V or -15V passed to the resistor chain as 1 or -1 with zero being the rest position.
For now, logic fast enough to do appx. 12MHz without issues and able to handle 30V doesn't exist.
I also found that Op-Amp's really dislike RF noise on the inputs. using a passive filter to remove as much as possible from reaching active circuitry helps. Filtering the "noise shaping" noise, at least above ~50...10kHz helps.
I found such issues to be both audible and possible to be measured indirectly.
BUT didn't you insist there is no problem?
Thor
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Using Amanero means no galvanic isolation of USB. Amanero can be made better by running it from clean, isolated +5v power instead of USB power. However, CM noise on the USB bus from the PC is still often a problem. I2SoverUSB with two isolated +5v supplies is better and clocking better but still not great. External clocking of I2SoverUSB with good clocks, carefully powered and buffered (and no ferrites) is better yet. Reclocking I2S data at some point before the dac or just at the dac also can help. Every little thing matters.
Anyway, I have SOA clocks from Andrea and from Acko, but to test what consumer grade clocks can do I just designed a little clock board using accusilicon 45/49MHz clocks. NC7SZ74K8X divides them by two to get 22/24MHz and 6dB less phase noise. Buffering is done by NB3L553. LT1763 clock voltage regulator is loaded with a 10R, 1.5W metal film resistor. Most of the caps are Rubycon:
https://www.digikey.com/en/products/detail/rubycon/1189-4323-KIT/9817213?s=N4IgTCBcDaIE4FcBGBPAxgewHYAIDOAtgCY4BmAlgDYE5oCGADniALoC+QA
Board is 4-layer with a strategy of trying to keep bypass currents on surface fill so as to keep the ground plane on layer-2 cleaner than it might otherwise be. Can't sell it or give it away, but the basic concept is probably clear.
The stuff about opamps and filtering was known years ago by Allo and me. There are tradeoffs with filtering before I/V stage however, but probably more so with CMOS dac ICs since the internal resistors are so nonlinear.
John Westlake also talked about Little Logic and using the smallest SMD packages to minimize inductance.
Andrea Mori has a version of a RTZ DSD dac that goes +1 and -1 with 0 in the middle. Doesn't swing a lot of volts though.
Turns out very many things are audible. They can all be measured to varying extents, but the numbers may sometimes be small-ish.
So, having Thor here, a technical guy with ears, is kind of refreshing for me.
Anyway, I have SOA clocks from Andrea and from Acko, but to test what consumer grade clocks can do I just designed a little clock board using accusilicon 45/49MHz clocks. NC7SZ74K8X divides them by two to get 22/24MHz and 6dB less phase noise. Buffering is done by NB3L553. LT1763 clock voltage regulator is loaded with a 10R, 1.5W metal film resistor. Most of the caps are Rubycon:
https://www.digikey.com/en/products/detail/rubycon/1189-4323-KIT/9817213?s=N4IgTCBcDaIE4FcBGBPAxgewHYAIDOAtgCY4BmAlgDYE5oCGADniALoC+QA
Board is 4-layer with a strategy of trying to keep bypass currents on surface fill so as to keep the ground plane on layer-2 cleaner than it might otherwise be. Can't sell it or give it away, but the basic concept is probably clear.
The stuff about opamps and filtering was known years ago by Allo and me. There are tradeoffs with filtering before I/V stage however, but probably more so with CMOS dac ICs since the internal resistors are so nonlinear.
John Westlake also talked about Little Logic and using the smallest SMD packages to minimize inductance.
Andrea Mori has a version of a RTZ DSD dac that goes +1 and -1 with 0 in the middle. Doesn't swing a lot of volts though.
Turns out very many things are audible. They can all be measured to varying extents, but the numbers may sometimes be small-ish.
So, having Thor here, a technical guy with ears, is kind of refreshing for me.
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Dear Thor,
Your posting could well be generated by AI, and maybe you even did.
Just a stream of fancy sounding words.
I’m really impressed.
Hans