In case of any interest, opened a new thread for discussion of the clock board project: https://www.diyaudio.com/community/threads/general-purpose-dac-clock-board.413001/#post-7688633
@ThorstenL From what series and brand are your favourite low-distortion inductors? (I think you mentioned it somewhere in this thread, but I can't find it back...)
Marcel,
No specific brand/type. You want an inductor rated for a lot of DC current. This means the magnetic material with be less inductance per turn and less distortion at a given level.
There are many 10-12mm shielded inductors from both major makers like TDK, Tayo Yuden, Murata, Samsung etc.
I used items custom made for iFi to my spec by an outfit in Shenzhen called Cybermax. They all only "cook with water".
So give it a space for a 10mm X 4...6mm SMD inductor and pick a line that has the right items in terms of value and size. I usually start with TDK catalogue.
In my application I came of the DAC with around 900 Ohm per phase, 3.2V P-P differential. I applied a single point servo "pulldown" on +/-15V to get the output from 1.6V to 0V and bootstrapped the pull down resistor designed fog -12V on the Op-Amp output.
So I was drawing around 2mA but my AC Load Impedance was 20k differential.
If you ask me, you want around 10 times signal current or more.
Bruno recently "discovered" inductor distortion (especially Hysteresis) in class D Amp's and promptly and valiantly decided to add another 100dB of feedback to "fix" this.
We should also note that in pure voltage mode (infinite load impedance) and in pure current mode (true dead short on out) our inductor doesn't distort.
Thor
No specific brand/type. You want an inductor rated for a lot of DC current. This means the magnetic material with be less inductance per turn and less distortion at a given level.
There are many 10-12mm shielded inductors from both major makers like TDK, Tayo Yuden, Murata, Samsung etc.
I used items custom made for iFi to my spec by an outfit in Shenzhen called Cybermax. They all only "cook with water".
So give it a space for a 10mm X 4...6mm SMD inductor and pick a line that has the right items in terms of value and size. I usually start with TDK catalogue.
In my application I came of the DAC with around 900 Ohm per phase, 3.2V P-P differential. I applied a single point servo "pulldown" on +/-15V to get the output from 1.6V to 0V and bootstrapped the pull down resistor designed fog -12V on the Op-Amp output.
So I was drawing around 2mA but my AC Load Impedance was 20k differential.
If you ask me, you want around 10 times signal current or more.
Bruno recently "discovered" inductor distortion (especially Hysteresis) in class D Amp's and promptly and valiantly decided to add another 100dB of feedback to "fix" this.
We should also note that in pure voltage mode (infinite load impedance) and in pure current mode (true dead short on out) our inductor doesn't distort.
Thor
Marcel,
The proposed circuit performs well.
Since I did not have the BC639, I used a ZTX851, all other transistors as specified.
1) With the ZTX851, the 22uH inductor gave a slight hick-up around 8Mhz, without inductor the FR showed a steady downslope.
2) With this circuit there is no real SE output for those convinced that SE is superior.
3) Using the ZTX851, noise was 8.5dB lower as with the OPA2228.
Hans
P.S. I forgot to mention that CMRR is just ca. -70dB with perfectly matched transistors and resistors up to 1Mhz with a -50dB peak at 100Khz.
Do you think this is good enough ?
The proposed circuit performs well.
Since I did not have the BC639, I used a ZTX851, all other transistors as specified.
1) With the ZTX851, the 22uH inductor gave a slight hick-up around 8Mhz, without inductor the FR showed a steady downslope.
2) With this circuit there is no real SE output for those convinced that SE is superior.
3) Using the ZTX851, noise was 8.5dB lower as with the OPA2228.
Hans
P.S. I forgot to mention that CMRR is just ca. -70dB with perfectly matched transistors and resistors up to 1Mhz with a -50dB peak at 100Khz.
Do you think this is good enough ?
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Marcel,
Did you consider a folded cascode FDA type structure?
If the output buffers are fast enough, this should be unconditionally stable as there is just a single gain stage.
I might be tempted to use PNP inputs (lower noise) and Dual N-Channel FET's for the cascading after flipping everything.
Or perhaps, to be ultra annoying, how about a dual triode as Cascode element?
Thor
I have a cascoded differential pair as second stage, rather than two voltage followers - a differential pair because it reduces the signal swing at the first stage's output and cascoded because a back-of-an-envelope calculation based on Cherry and Hooper's differential gain equations showed that Early effect would be a dominant source of distortion in the second stage. Except for the right half plane zero and the polarity, there is not much difference between the response of a current-driven emitter follower with a capacitor to ground and a current-driven common-emitter stage with Miller compensation.
Regarding the polarity, with a finite tail current source impedance, my circuit has inherent positive common-mode feedback while one with a voltage follower second stage would have had inherent negative common-mode feedback. For my circuit, the common-mode loops need to be strong enough to prevent common-mode latch-up or instability. It is not a very big disadvantage, but it is a disadvantage.
In any case, the common-mode stability issues I had were due to an incorrect calculation of the common-mode loop transfer.
Regarding the polarity, with a finite tail current source impedance, my circuit has inherent positive common-mode feedback while one with a voltage follower second stage would have had inherent negative common-mode feedback. For my circuit, the common-mode loops need to be strong enough to prevent common-mode latch-up or instability. It is not a very big disadvantage, but it is a disadvantage.
In any case, the common-mode stability issues I had were due to an incorrect calculation of the common-mode loop transfer.
The BC639 and BC640 have far lower base resistances than the BC546 to BC560 family, but those have more current gain and somewhat higher fT's at a given current. I've used the BC639/BC640 where voltage noise matters and the BC546...BC560 family everywhere else.
By the way, I originally wanted to use an antiparallel connection of PNP transistors for the input stage, but settled for antiseries (that is, a differential pair) because I found no practical way to bias the antiparallel version. With a PNP differential pair, the circuit was essentially the present circuit upside down: PNPs and NPNs and positive and negative supply swapped compared to the present circuit.
When I later started thinking about what might go wrong if one supply starts up faster than the other, I figured that the current sources from the positive supply might blow up the DAC core if they would become active before the negative supply came up (reference supply lifted via the ESD and drain-bulk diodes in the shift register). I could fix that by either adding some circuitry to prevent the current sources from starting without a negative supply or putting the whole thing upside down and settle for an NPN differential pair input stage.
Some rough noise measurements showed that the base resistance of the NPNs was low enough not to dominate the noise, so I simply went for the NPN input pair version.
When I later started thinking about what might go wrong if one supply starts up faster than the other, I figured that the current sources from the positive supply might blow up the DAC core if they would become active before the negative supply came up (reference supply lifted via the ESD and drain-bulk diodes in the shift register). I could fix that by either adding some circuitry to prevent the current sources from starting without a negative supply or putting the whole thing upside down and settle for an NPN differential pair input stage.
Some rough noise measurements showed that the base resistance of the NPNs was low enough not to dominate the noise, so I simply went for the NPN input pair version.
Interesting. I would have expected a small aberration around the corner frequency of the zero determined by 22 uH and two times 150 ohm, but that should be roughly 2.2 MHz.
You can still use only one output if you want to.
At first sight, I'd say it is still good enough to ensure passive filter component tolerances will dominate. Did you look at the ratio of the differential and common-mode transfers?
It's just a frequency compensation component inside a feedback loop. It should be far less critical than the 100 uH inductors.
Yes, but the signal at one output will still be determined by both Firdac outputs, other than in the current filter where one output has the processed info of just one Firdac.
No, I looked at the ratio of output versus common mode input.
Hans
Wasn’t that exactly what Mark did and maybe others also ?
I’ll show the CMRR simulation tomorrow.
That will answer the question.
Hans
With the latest change to the reclocker board here, Marcel's dac is sounding better than ever in SE mode. Only output stage consists of DC blocking caps and the transformers in my line amp. Starting to rival more serious dacs (at least with the 120R resistors installed across the 22uf shift register bypass caps, the only mod to Marcel's dac).
Of course. So your point is that compared to the original filter, it is more difficult to modify this filter such that the single-ended output signals each depend almost exclusively on one of the FIRDACs. That's true, of course.
Not a problem. Either the new filter will sound great or at least some of us will keep looking into other solutions.
Just to be clear, the reason for using SE instead of balanced is purely a practical one. Theory says balanced is better. Experience shows that if various design problems are solved then SE may end up sounding better to most people. Also, whenever SE is suggested it is quite normal for EE's to scoff at the idea. I did at first. Andrea did at first, etc. Of course we all scoff because it goes against theory.
Just to be clear, the reason for using SE instead of balanced is purely a practical one. Theory says balanced is better. Experience shows that if various design problems are solved then SE may end up sounding better to most people. Also, whenever SE is suggested it is quite normal for EE's to scoff at the idea. I did at first. Andrea did at first, etc. Of course we all scoff because it goes against theory.
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