Simultaneous output Frontend for TDA1541 (and or Universal Multibit DAC) using discrete logic - Collaborators wanted

Ok, so I have been thinking, if there is a way to get a simple Sample Rate indication using discrete logic.

Ok, my conclusion, it ain't that simple. Oh sod it, it actually is.

Elsewhere I proposed to have 24.576MHz & 22.5792MHz clocks on our DAC PCB. With the 24.576MHz as reference clock, we can use 7pcs of generic IC's (maybe less, will think a bit more on details) to get a reliable detection:

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The first trick is to divide the 24.576MHz crystal clock to 8.192MHz.

I will use an 8-Bit counter and latch (74HC590) to provide the counter that counts the crystal clock cycles (divided by 3) within 1/2 wordclock cycle. The Wordclock is used to reset the counter and is delayed and inverted with a logic gate.

When the Word clock goes high, the result is latched in the output Register and the counter is held in reset until the wordclock goes low again, at which point our counter increments.

For 48kHz we count 8.192MHz/48kHz/2 = 85 Cycles, for 96kHz we count 42 Cycles and for 192kHz we count 21.

Thus:

A count of > 16 is 4 X
A count of > 32 is 2 X
A count of > 64 is 4 X

So we just look at corresponding output and add some interlock logic to get clean indication. At this point we have 1X/2X/4X indication with 4 IC's, compared to 3 IC's for the RC Timer and latches.

If we do not need to be that accurate and want something basic, the RC timer option is simple and valid.

But I WANT 44.1/48k detection and reliable, so the output can run on crystal clocks.


The 44.1/48 base detection is hampered by the fact that the specific 0x18 pattern that indicates the boundary between 44.1kHz and 48khz at 46.05kHz shifts by one bit each time the sample rate doubles this makes a hardware solution challenging, here code rules (count >> 1; would do the trick).

Hardly elegant, but dividing the Word clock by 1 for 1X, by 2 for 2X and 4 for 4X gets a constant word clock frame width. Two 74HC74 flip flops and a 4-Way multiplexer handle that part. Then back to another 74HC590.

Thus our 0X18 pattern stays in one place and simple NAND gate will have L on the output if the count reached 0x18 and yes, with 48kHz the bit pattern shows 0X08 for the count, so we can reliably tell 44.1kHz from 48kHz (and 88.2/96/176.4/192k).

I will look more if there is a suitable common IC that can simplify the divider stage. I have doubts I will find anything.

With a total of 7pcs of 14....16 Pin 74HC IC's are are not that outrageous. note, these are all considered "noisy", they should have a separate PCB Island with a minimal "bridge" to the main PCB and a completely in depended power supply for all auxiliary circuitry.

We could do all this in a MCU of course. Probably for less.

Thor