I don't like and don't use the resistor in lieu of the fuses in the power rails.
They are in effect a very slow blow fuse. The damage is already done if the 100r burst into flames. Higher wattage resistors allow even more damage.
The bulb tester is far better at protecting from damage while you check for correct operation/wiring.
But the bulb tester only works for zero output bias or very low output bias Just enough to prove that the Bias generator is supplying a controllable bias voltage.
Fuse holder resistors are good for checking front end quiescent currents.
They are in effect a very slow blow fuse. The damage is already done if the 100r burst into flames. Higher wattage resistors allow even more damage.
The bulb tester is far better at protecting from damage while you check for correct operation/wiring.
But the bulb tester only works for zero output bias or very low output bias Just enough to prove that the Bias generator is supplying a controllable bias voltage.
Fuse holder resistors are good for checking front end quiescent currents.
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The idea of the fuse resistor was to provide a convenient way to measure bias - this is how Greg does it although in his case the resistor is only installed to set the bias. I've abandoned that method, it's simply easier to measure the current in the power supply.
I had the oscilloscope in action - found some oscillations. At < 30 mA per FET the signal at the output is clean. At 50mA per FET there are some lovely 1.2MHz sine waves although the bias is stable and everything else seems well behaved. Above 65mA per FET additional nasties start up and it all goes to hell.
This evening I'll try to sort this out. When I think about what has changed since using 20V supplies I have some candidates to look into, such as lead dress & local power rail decoupling - I have a pair of electrolytics but I didn't install the small bypass caps. Also the higher rail voltage will have the effect of lowering the intrinsic FET capacitances and I wonder if reduced Cgd should be augmented externally to provide some stabilization - I included the pads on the pcb just for this purpose.
I had the oscilloscope in action - found some oscillations. At < 30 mA per FET the signal at the output is clean. At 50mA per FET there are some lovely 1.2MHz sine waves although the bias is stable and everything else seems well behaved. Above 65mA per FET additional nasties start up and it all goes to hell.
This evening I'll try to sort this out. When I think about what has changed since using 20V supplies I have some candidates to look into, such as lead dress & local power rail decoupling - I have a pair of electrolytics but I didn't install the small bypass caps. Also the higher rail voltage will have the effect of lowering the intrinsic FET capacitances and I wonder if reduced Cgd should be augmented externally to provide some stabilization - I included the pads on the pcb just for this purpose.
Bigun,
Are you using small caps across the decoupling electrolytics? Isn't that often worse than good? I thought in adding a not so small cap like 1uF MKT. Worth it?
About the compensation cap: does the use of 2SC/SA small signals vs BCs changes the required compensation cap value? have you compared the 6pF value recommended by Greg with the 10pF?
Thanks.
Are you using small caps across the decoupling electrolytics? Isn't that often worse than good? I thought in adding a not so small cap like 1uF MKT. Worth it?
About the compensation cap: does the use of 2SC/SA small signals vs BCs changes the required compensation cap value? have you compared the 6pF value recommended by Greg with the 10pF?
Thanks.
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I was not able to solve the problem by adding 10nF bypass caps, or by adding gate-drain slow-down caps of 330pF to the FETs.
Bypass caps can be useless or worse if they contribute to ringing with the inductance of power rails but their addition appears to make no difference to the oscillations I see on my oscilloscope. The addition of gate-drain caps (before the gate stoppers) did reduce amplitude slightly, but did not fix the issue - I'm not overly surprised at that because Greg doesn't use this and his amp is stable.
I think the feedback cap at 10pF should not be too large to introduce a problem, I believe it's within the range that Greg has said is suitable for the amp.
Bypass caps can be useless or worse if they contribute to ringing with the inductance of power rails but their addition appears to make no difference to the oscillations I see on my oscilloscope. The addition of gate-drain caps (before the gate stoppers) did reduce amplitude slightly, but did not fix the issue - I'm not overly surprised at that because Greg doesn't use this and his amp is stable.
I think the feedback cap at 10pF should not be too large to introduce a problem, I believe it's within the range that Greg has said is suitable for the amp.
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I went back to check Greg's notes regarding the feedback cap. He recommends 5p to 7p, meaning I have too much. So I put two 10p in series to give me 5p total. I also removed the small bypass cap from the feedback shunt cap - just in case it was impacting the compensation. Now I don't see any oscillations, the bias is stable and I can adjust it to around 100mA per FET. I'm going to let it 'cook' for a little while to confirm all is good. Tomorrow if all is still good - I'll be able to listen to it 
p.s. I'm quite happy with my method for thermal compensation both schematic and mechanical - it reacts quickly. If I blow hard on the heatsink the bias current quickly rises to compensate and then slowly declines as the heatsink warms back up and then stabilizes again.
p.s. I'm quite happy with my method for thermal compensation both schematic and mechanical - it reacts quickly. If I blow hard on the heatsink the bias current quickly rises to compensate and then slowly declines as the heatsink warms back up and then stabilizes again.
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I went back to check Greg's notes regarding the feedback cap. He recommends 5p to 7p, meaning I have too much. So I put two 10p in series to give me 5p total. I also removed the small bypass cap from the feedback shunt cap - just in case it was impacting the compensation. Now I don't see any oscillations, the bias is stable and I can adjust it to around 100mA per FET. I'm going to let it 'cook' for a little while to confirm all is good. Tomorrow if all is still good - I'll be able to listen to it
Hi Bigun
The feedback caps you alluded to ---is this C3 across R23 in your schematic on the thread 8 ?
thanks
kp93300
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Hi kp93300, yes I was talking about C3 across R23 in my schematic.
Well I decided to do some square wave tests using the 1kHz signal from my oscilloscope. It produces an output of roughly 13.75V p-p with an input of 0.5V p-p so the gain is measuring at roughly 27.5 which isn't far off the calculated gain of 28.4.
With no load, the square wave is very clean, I can't see anything nasty - as to be expected. I tried a zero ohm load (accidentally) for about 1 second. The power transformer made some noises but the amp survived. So I did it again for another 1 second. Same noise, amp still works fine.
Into an 8 Ohm load I allowed the square wave to play longer and after 5 to 10 seconds it smoked the zobel resistor. It's an SMD device - perhaps not a good design choice. The resistor survived but it looks wounded.
Back to less demanding loads to investigate. Into a 1k load and then a 390R load the output is clean and no smoke.
Into a 20R load I now see distortion at the output, it looks like oscillations at around 170kHz. An output inductor doesn't help since this is a purely resistive load. I know square waves are unkind, but it's my understanding we want the amp to be stable with a 1kHz square wave so further work needed...
Well I decided to do some square wave tests using the 1kHz signal from my oscilloscope. It produces an output of roughly 13.75V p-p with an input of 0.5V p-p so the gain is measuring at roughly 27.5 which isn't far off the calculated gain of 28.4.
With no load, the square wave is very clean, I can't see anything nasty - as to be expected. I tried a zero ohm load (accidentally) for about 1 second. The power transformer made some noises but the amp survived. So I did it again for another 1 second. Same noise, amp still works fine.
Into an 8 Ohm load I allowed the square wave to play longer and after 5 to 10 seconds it smoked the zobel resistor. It's an SMD device - perhaps not a good design choice. The resistor survived but it looks wounded.
Back to less demanding loads to investigate. Into a 1k load and then a 390R load the output is clean and no smoke.
Into a 20R load I now see distortion at the output, it looks like oscillations at around 170kHz. An output inductor doesn't help since this is a purely resistive load. I know square waves are unkind, but it's my understanding we want the amp to be stable with a 1kHz square wave so further work needed...
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Well I have been rather busy on this amplifier. I have had some help from Greg, but the upshot is that I am not getting my amp to be fully stable on the higher rail voltages.
a) I have resolved the 170kHz oscillations due to wiring and earthing choices (my scope probe earth lead was part of the puzzle but not the only part). Solving this uncovered a 9MHz oscillation at lower level.
b) I have resolved the 9MHz oscillation. It is a spike (with associated phase change) in the PSRR of the amplifier. I found it through Spice simulations. The spike is below 0dB on the GB150 so isn't an issue there, but my TGM7 version has this spike reaching above 0dB so it becomes an accident waiting to happen. After further investigation I discovered that it is caused by the resistors I placed into the unused legs of the LTP collectors (long story, look at some work done by SandyK on this forum). I replaced them with jumpers. I believe that some base-collector capacitance to the rails at the IPS is needed for stability and the resistors botched it for me; I even added a little extra capacitance to the base-collector of the drivers which Spice told me had the effect of removing the PSRR spike without detrimental effects elsewhere. This resulted in no oscillations visible on my 'scope and I had clean square waves into an 8R load. But the zobel gets hot, even with no signal.
c) I was unable to resolve the hot zobel. It's a sign of oscillations, yet they are invisible on my 100MHz analogue (old) 'scope. Could be that the scope probe quenches them, or that they are beyond the bandwidth and noise limit of my scope. But the zobel was hot, both resistor and capacitor.
Unfortunately, before I could try too many cures I damaged the pcb. I think this is my cue to get on and redesign my pcb for better layout around the FETs, reducing some of the trace lengths (inductance), put more bypassing close to the FETs, and a perhaps a few other improvements.
a) I have resolved the 170kHz oscillations due to wiring and earthing choices (my scope probe earth lead was part of the puzzle but not the only part). Solving this uncovered a 9MHz oscillation at lower level.
b) I have resolved the 9MHz oscillation. It is a spike (with associated phase change) in the PSRR of the amplifier. I found it through Spice simulations. The spike is below 0dB on the GB150 so isn't an issue there, but my TGM7 version has this spike reaching above 0dB so it becomes an accident waiting to happen. After further investigation I discovered that it is caused by the resistors I placed into the unused legs of the LTP collectors (long story, look at some work done by SandyK on this forum). I replaced them with jumpers. I believe that some base-collector capacitance to the rails at the IPS is needed for stability and the resistors botched it for me; I even added a little extra capacitance to the base-collector of the drivers which Spice told me had the effect of removing the PSRR spike without detrimental effects elsewhere. This resulted in no oscillations visible on my 'scope and I had clean square waves into an 8R load. But the zobel gets hot, even with no signal.
c) I was unable to resolve the hot zobel. It's a sign of oscillations, yet they are invisible on my 100MHz analogue (old) 'scope. Could be that the scope probe quenches them, or that they are beyond the bandwidth and noise limit of my scope. But the zobel was hot, both resistor and capacitor.
Unfortunately, before I could try too many cures I damaged the pcb. I think this is my cue to get on and redesign my pcb for better layout around the FETs, reducing some of the trace lengths (inductance), put more bypassing close to the FETs, and a perhaps a few other improvements.
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The 9 mHz problems are also present in the simulation of your circuit where it shows guite a big gain peaks paired with a large phaseshift. Something need to change in the way the circuit is compensated.
In simulation is seems beneficial to not hav the C-13 compensation cap in the FB network, it seems to introduce a lot of phase shifts and gain peeking
/M
In simulation is seems beneficial to not hav the C-13 compensation cap in the FB network, it seems to introduce a lot of phase shifts and gain peeking
/M
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My spice simulation may have some issues - but I'm attaching the file for your interest. The plot shows the PSRR (with respect to the +ve rail).
I've attached the spice file so you can run the simulation. Note that it uses device models from Bob Cordell; I'd like to acknowledge his copyright.
I've attached the PSRR plot generated by the spice file. There are three curves in total (look at the solid lines). A PSRR of 0dB means that the noise on the power rail appears equally on the output of the amplifier. A PSRR of -60dB or better is a minimum requirement and is easily met over the audio frequency range. What I am showing here is the very high frequencies where there is an issue with a peak. A high peak here can result in oscillations. The current flowing at the output is drawn through the power supply and therefore the signal at the output can appear as a voltage drop in the power supply. And a phase change can result in this signal being amplified by the amplifier - positive feedback and resonance. This is how I am looking at it. A peak in the PSRR usually also has a sudden phase (dashed lines in the plot) change - indicative of resonance.
My model does not include stray capacitance and parasitic inductance, so the results are clearly approximate. But since I observed oscillations in the general range of the predicted frequency and was able to quench them based on the changes indicated by the simulation I like to think it's pretty good.
Looking at the PSRR plot:
Greg's GB150 is the blue curve. A slight peak at 10MHz. My TGM7 is the green curve and there are two versions. As-built the PSRR is the top green curve with the huge resonance spike in the range 7MHz to 8MHz. Nasty. After removing the 3k resistors from the unused collector legs of the LTPs I get the lower green curve. It is now closer to the baseline GB150 behaviour.
So the problem is eliminated when I remove these resistors and replace them with jumpers. No changes to the compensation are required.
I've attached the spice file so you can run the simulation. Note that it uses device models from Bob Cordell; I'd like to acknowledge his copyright.
I've attached the PSRR plot generated by the spice file. There are three curves in total (look at the solid lines). A PSRR of 0dB means that the noise on the power rail appears equally on the output of the amplifier. A PSRR of -60dB or better is a minimum requirement and is easily met over the audio frequency range. What I am showing here is the very high frequencies where there is an issue with a peak. A high peak here can result in oscillations. The current flowing at the output is drawn through the power supply and therefore the signal at the output can appear as a voltage drop in the power supply. And a phase change can result in this signal being amplified by the amplifier - positive feedback and resonance. This is how I am looking at it. A peak in the PSRR usually also has a sudden phase (dashed lines in the plot) change - indicative of resonance.
My model does not include stray capacitance and parasitic inductance, so the results are clearly approximate. But since I observed oscillations in the general range of the predicted frequency and was able to quench them based on the changes indicated by the simulation I like to think it's pretty good.
Looking at the PSRR plot:
Greg's GB150 is the blue curve. A slight peak at 10MHz. My TGM7 is the green curve and there are two versions. As-built the PSRR is the top green curve with the huge resonance spike in the range 7MHz to 8MHz. Nasty. After removing the 3k resistors from the unused collector legs of the LTPs I get the lower green curve. It is now closer to the baseline GB150 behaviour.
So the problem is eliminated when I remove these resistors and replace them with jumpers. No changes to the compensation are required.
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I'm not too sure that the way I examine the phase stability with an open loop gain plot is quite correct and would love to be taught better if possible.
I've attached the spice file I used for looking at the OLG and the plot that it produces. I am looking at the ratio of the voltages either side of the OLG signal generator that I've inserted into the global feedback loop.
It shows this amplifier has a scary amount of gain at high frequencies and a scary amount of gain at audio frequencies. If I'm looking at this correctly, I want to home in on the phase change (dashed lines) that accumulated before the open loop gain (solid lines) drops below 0dB. It looks like a 100 degree change between 1kHz and 10MHz. Looks OK to me.
However, without stray capacitance and parasitic inductances this is likely way over-simplified.
I've attached the spice file I used for looking at the OLG and the plot that it produces. I am looking at the ratio of the voltages either side of the OLG signal generator that I've inserted into the global feedback loop.
It shows this amplifier has a scary amount of gain at high frequencies and a scary amount of gain at audio frequencies. If I'm looking at this correctly, I want to home in on the phase change (dashed lines) that accumulated before the open loop gain (solid lines) drops below 0dB. It looks like a 100 degree change between 1kHz and 10MHz. Looks OK to me.
However, without stray capacitance and parasitic inductances this is likely way over-simplified.
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The slope of the gain line is indicative of phase.
At the zero crossing, it is said that the slope must be less than 9dB/octave.
Many suggest this should be less than 6dB/octave for a more adequate phase margin.
Your slope is certainly steepening as it approaches and passes through the unity gain frequency.
+105dB @ LF is in the normal range.
10MHz for unity gain is in the normal range.
I don't understand the reported 360degrees @ unity gain.
At the zero crossing, it is said that the slope must be less than 9dB/octave.
Many suggest this should be less than 6dB/octave for a more adequate phase margin.
Your slope is certainly steepening as it approaches and passes through the unity gain frequency.
+105dB @ LF is in the normal range.
10MHz for unity gain is in the normal range.
I don't understand the reported 360degrees @ unity gain.
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I haven't much experience with these guidelines but it's good to know. I will probably design some options into the next round of the pcb to allow me to reduce the gain at high frequency, I'll see if I can find a method (simulated) that reduces this steepening - although I do suspect the simulation is getting less accurate out there where stray impedances are not taken into account.
The phase at unity gain - I don't think this matters too much, it's the cumulative phase change over frequency that I worry about rather than the absolute phase.
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Well I got to thinking about the amp design and whether to fiddle with it a bit more. The 10MHz resonance appears in simulations to be made worse because of the LTP input. Extra devices with phase shift catches up with you in end. So after being inspired by reading Gaborbela's thread I got to thinking about a singleton input, or CFA. I remembered something was proposed by fab here: http://www.diyaudio.com/forums/solid-state/239443-cfb-ska-hybrid-vssa-ska-amps-concept.html
I've been looking at this in more detail. My version is based more tightly on the GB150 but is pretty much the same otherwise. And I am now thinking that I may use this approach and re-spin my pcb for it.
It appears that the OLG has better margin at unity gain. The only downside is the need for larger caps in the feedback network and overall lower PSRR. The LTP simply does better with higher common mode rejection of noise on the rails.
I like that the CFA has a low impedance feedback node, so it won't pick up as much stray signal - perhaps more tolerant of pcb and chasis layout.
Trouble is with this symmetrical CFA type of topology is the potential for terrible bias stability with respect to temperature - which might kill this idea before it gets off the drawing board.
I've been looking at this in more detail. My version is based more tightly on the GB150 but is pretty much the same otherwise. And I am now thinking that I may use this approach and re-spin my pcb for it.
It appears that the OLG has better margin at unity gain. The only downside is the need for larger caps in the feedback network and overall lower PSRR. The LTP simply does better with higher common mode rejection of noise on the rails.
I like that the CFA has a low impedance feedback node, so it won't pick up as much stray signal - perhaps more tolerant of pcb and chasis layout.
Trouble is with this symmetrical CFA type of topology is the potential for terrible bias stability with respect to temperature - which might kill this idea before it gets off the drawing board.
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It is not dead, it is just postponed to a later time since I am convinced I can succeed to stabilize it in the end.
Fab
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Well I've been playing with this in spice a bit more. I think it can be kept stable with the temperature comp scheme I've been using since I can vary the sensitivity of the temperature comp.
My remaining concern is relatively low PSRR, only -54dB. This is 20dB to 30dB worse than the VFA version - that is a LOT. This puts more onus on the power supply design, favouring dual rectifier to reduce differential ripple across the power rails for example.
Distortion profiles for the CFA and VFA versions are likely to be the same. The differences are going to be subtle if both are implemented well. The CFA looks simpler on paper but this might be offset by extra demands on the power supply.
I understand that CFA offers potential advantages in terms of slew rate and high bandwidth but the VFA version has just as much bandwidth in the base design and I'm not sure it suffers from slew rate issues. So why choose the CFA version ? (I have little patience for the CFA-hype on this forum of late).
My remaining concern is relatively low PSRR, only -54dB. This is 20dB to 30dB worse than the VFA version - that is a LOT. This puts more onus on the power supply design, favouring dual rectifier to reduce differential ripple across the power rails for example.
Distortion profiles for the CFA and VFA versions are likely to be the same. The differences are going to be subtle if both are implemented well. The CFA looks simpler on paper but this might be offset by extra demands on the power supply.
I understand that CFA offers potential advantages in terms of slew rate and high bandwidth but the VFA version has just as much bandwidth in the base design and I'm not sure it suffers from slew rate issues. So why choose the CFA version ? (I have little patience for the CFA-hype on this forum of late).
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Lots of peoples - including myself - have reported good soundstage character of CFA amps. For the low PSRR compared to VSSA, it seems that it does not bother fans of VSSA, PASS, Accuphase, some Marantz, Hiraga, Bonsai NX, .. To name a few...
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The VSSA is very good (basis for my TGM5), in fact it does not have low PSRR, the output is emitter/source follower. The VAS is isolated from the supply with RC filter. This allows very good PSRR with these amplifiers. Bonsai's NX is the same, it has good PSRR.
However, the SKA topology is different and in terms of PSRR it suffers from being common Drain output so it has lower PSRR with a CFA input stage. The Hiraga (the small symmetric Class A) has similar topology limitations with poor PSRR, which is one reason why Hiraga used car batteries when he made it. Nelson shows how to make a regulated supply for some of his DIY amps - due to low PSRR.
Interesting observation you made. Why would the sound stage be different ? - I would be looking at the phase response. The FR and OLG gain plots for SKA with VSA or CFA show me something about the phase response - can't see much of a difference. I really don't have any experience with this, no idea how to correlate sound stage with the amplifier design.
It would be interesting if anybody has heard both the SKA GB150 and also a VSSA....
p.s. PauloT says of the GB150 "Outstanding dynamics, huge soundstage, impressive transparency!!!" http://www.diyaudio.com/forums/solid-state/238593-ska-gb150d-now-public-domain-7.html#post3665691
However, the SKA topology is different and in terms of PSRR it suffers from being common Drain output so it has lower PSRR with a CFA input stage. The Hiraga (the small symmetric Class A) has similar topology limitations with poor PSRR, which is one reason why Hiraga used car batteries when he made it. Nelson shows how to make a regulated supply for some of his DIY amps - due to low PSRR.
Interesting observation you made. Why would the sound stage be different ? - I would be looking at the phase response. The FR and OLG gain plots for SKA with VSA or CFA show me something about the phase response - can't see much of a difference. I really don't have any experience with this, no idea how to correlate sound stage with the amplifier design.
It would be interesting if anybody has heard both the SKA GB150 and also a VSSA....
p.s. PauloT says of the GB150 "Outstanding dynamics, huge soundstage, impressive transparency!!!" http://www.diyaudio.com/forums/solid-state/238593-ska-gb150d-now-public-domain-7.html#post3665691
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Common for types of Hiraga and the likes is the common drain output, that's why they demand such extensive filtering, but if you ever heard an good Hiraga, then you know you're in for a treat. this here holds even more promise, as it can be scaled to larger voltage rails and outputs. I think it deserves exploration, maybe even just as a frontend for a current dumping output, if you do that extra diodes and caps can prevent rail sag.