There are many details I still need to work out, but I think I found a way to use TE0630 LX45 FPGA boards for the valve DAC.
As you may or may not remember, I use a rather extreme interpolation chain. The 200 kHz sample rate signal from the SRC4392 first gets interpolated to 600 kHz and then all the way up to 3 MHz with filters with > 140 dB stop band suppression before being put into a zero-order hold and then into the sigma-delta modulator.
Besides its chaotic single-bit mode, the sigma-delta modulator has a PWM4 mode, with a five-level quantizer running at one quarter of the 27 MHz clock rate (so 6.75 MHz), and a PWM8 mode, with a nine-level quantizer running at one eighth of the clock rate (3.375 MHz). As 3.375 MHz and 6.75 MHz are not integer multiples of 200kHz, you can get aliasing and need good filters to suppress that.
When I change it into PWM5 and PWM9, so a six-level quantizer at one fifth of 27 MHz and a ten-level quantizer at one ninth of 27 MHz, the quantizers run at an integer multiple of 200 kHz and of 600 kHz and I can leave out the interpolation to 3 MHz without any aliasing at all. Imaging around 600 kHz is suppressed to some extent by the signal transfer function of the sigma-delta and by the analogue post filter, besides, the frequency is so high that even bats couldn't hear it.
I've done some experiments and when I cut out the interpolation filter to 3 MHz, reduce the stopband rejection of the interpolation filter to 600 kHz and reduce the FIR clock frequency from 216 MHz to 189 MHz, then the design fits into an LX45 FPGA of speed grade 2.
As you may or may not remember, I use a rather extreme interpolation chain. The 200 kHz sample rate signal from the SRC4392 first gets interpolated to 600 kHz and then all the way up to 3 MHz with filters with > 140 dB stop band suppression before being put into a zero-order hold and then into the sigma-delta modulator.
Besides its chaotic single-bit mode, the sigma-delta modulator has a PWM4 mode, with a five-level quantizer running at one quarter of the 27 MHz clock rate (so 6.75 MHz), and a PWM8 mode, with a nine-level quantizer running at one eighth of the clock rate (3.375 MHz). As 3.375 MHz and 6.75 MHz are not integer multiples of 200kHz, you can get aliasing and need good filters to suppress that.
When I change it into PWM5 and PWM9, so a six-level quantizer at one fifth of 27 MHz and a ten-level quantizer at one ninth of 27 MHz, the quantizers run at an integer multiple of 200 kHz and of 600 kHz and I can leave out the interpolation to 3 MHz without any aliasing at all. Imaging around 600 kHz is suppressed to some extent by the signal transfer function of the sigma-delta and by the analogue post filter, besides, the frequency is so high that even bats couldn't hear it.
I've done some experiments and when I cut out the interpolation filter to 3 MHz, reduce the stopband rejection of the interpolation filter to 600 kHz and reduce the FIR clock frequency from 216 MHz to 189 MHz, then the design fits into an LX45 FPGA of speed grade 2.
Wow that would be incredible! Not only the cost saving, but Trenz has lots of the LX45 boards available.
I was in some FPGA Discords today discussing the LX150, but the speed grade issue was insurmountable. The people that were helping me said that 216MHz is kinda at the limit of the Spartan 6 anyway.
I was in some FPGA Discords today discussing the LX150, but the speed grade issue was insurmountable. The people that were helping me said that 216MHz is kinda at the limit of the Spartan 6 anyway.
This thread is somewhat like watch a TV soap opera...lots going on...ups and downs!
As someone with the LX75 module I think that making it work on the LX45 is a good thing (not pressuring you Marcel - getting to LX45 working sounds like a lot of work to me). The Trenz website now has a header saying 35 week delay on several items, but at the moment there are 121 LX45 in stock. There are people in my kneck of the woods that wish to hear my ValveDac or at least my impressions of the sound of the ValveDac before embarking on the build themselves and not having to wait till the end of the year for FPGA may also assist their decision process.
Apparently the final little parts to finish my build are onboard with the courier for delivery today. With any luck the magic smoke will stay away and I will have my ValveDac operational over the weekend.
As someone with the LX75 module I think that making it work on the LX45 is a good thing (not pressuring you Marcel - getting to LX45 working sounds like a lot of work to me). The Trenz website now has a header saying 35 week delay on several items, but at the moment there are 121 LX45 in stock. There are people in my kneck of the woods that wish to hear my ValveDac or at least my impressions of the sound of the ValveDac before embarking on the build themselves and not having to wait till the end of the year for FPGA may also assist their decision process.
Apparently the final little parts to finish my build are onboard with the courier for delivery today. With any luck the magic smoke will stay away and I will have my ValveDac operational over the weekend.
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Well, it's over almost before it began. I muffed it. Friday afternoon, knock off work and started the final push to fire up the ValveDac. Less than 5 minutes into it I had shimmed the mezzanine standoffs to the correct height with washers and thought to do a continuity check between each of the metal standoffs to make sure they were not connected to ground on both levels so I pulled the FPGA out of the tight fitting sockets one more time, was less careful on this occasion and managed to lift some pcb traces connected to the ValveDac mezzanine connector. Oh no!
From what I can see no traces are broken but it is a sub-ideal situation and I have no choice but to de-populate the pcb as best I can and transfer the components to a clean board (got plenty of those!). Rather than desolder/resolder them I will probably just re-order all the SMD components and pin headers from Mouser and with any luck have them in a week or two.
Will get onto that now.
From what I can see no traces are broken but it is a sub-ideal situation and I have no choice but to de-populate the pcb as best I can and transfer the components to a clean board (got plenty of those!). Rather than desolder/resolder them I will probably just re-order all the SMD components and pin headers from Mouser and with any luck have them in a week or two.
Will get onto that now.
Today I first got sound using an LX45 module, with my solid-state DAC that is supposed to be compatible with the valve DAC. There is still a set-up time issue related to the CDIN line of the DIX4192 to solve and I need to tweak some coefficients because it now regularly runs into integrator clipping when using the loud mode. I guess the first integrator needs a bit more headroom now that the images around 600 kHz are not suppressed anymore at the sigma-delta modulator input.
This morning the JTAG programming cable refused to work, later it worked fine, no idea what changed. Then the DAC didn't do anything at all, but that was because I had forgotten to short the R102 pads on the FPGA module.
This morning the JTAG programming cable refused to work, later it worked fine, no idea what changed. Then the DAC didn't do anything at all, but that was because I had forgotten to short the R102 pads on the FPGA module.
It's not the aliases, apparently I introduced some bug in the sigma-delta modulator that causes asymmetrical behaviour. It can handle much larger positive than negative input signal excursions without integrator clipping. Fortunately it can be simulated with reasonably short run times, so I should be able to figure it out.
There are a couple of technical advantages and disadvantages, but they are all very minor:
The LX45 version has less suppression of far ultrasonic images (> 100 kHz, particularly 500 kHz...700 kHz).
The LX45 version has slightly more out-of-band quantization noise in the PWM modes.
It probably has a slightly better signal-to-noise ratio over the audio band in the PWM modes.
Aliasing effects in the quantizer of the sigma-delta modulator in the PWM modes are completely absent in the LX45 variant, rather than negligibly small.
The chaotic sigma-delta mode of the LX75 versions 1, 2 and 2.1 has a time-varying noise level when playing absolute silence, I implemented a workaround for that in the LX45 version.
The LX45 version has less suppression of far ultrasonic images (> 100 kHz, particularly 500 kHz...700 kHz).
The LX45 version has slightly more out-of-band quantization noise in the PWM modes.
It probably has a slightly better signal-to-noise ratio over the audio band in the PWM modes.
Aliasing effects in the quantizer of the sigma-delta modulator in the PWM modes are completely absent in the LX45 variant, rather than negligibly small.
The chaotic sigma-delta mode of the LX75 versions 1, 2 and 2.1 has a time-varying noise level when playing absolute silence, I implemented a workaround for that in the LX45 version.