D4 is in the wrong place, you need to protet Vgs of the bottom MOSFET.
Also, paralleling MOSFETs will require source resistors (0R22 att least). The question remains why use two pairs - it is doubtful the VS will drive two of them on top.
Alternatively, why not use larger MOSFETs, say IRFP250, single pair. At least no current sharing problems exist.
Also, paralleling MOSFETs will require source resistors (0R22 att least). The question remains why use two pairs - it is doubtful the VS will drive two of them on top.
Alternatively, why not use larger MOSFETs, say IRFP250, single pair. At least no current sharing problems exist.
as Ranc has said, saving the VAS from blowing up does matter when a transient spike arrives at the Zener.
If the Gate Stopper is inserted between the VAS and the Zener, then the VAS current is limited and the VAS survives.
Saving money on a few extra Zeners seems to pale into insignificance !
Ranchu, BD140 Vcemax is insufficuent for positions Q5 and Q7 if the supply voltage is +-50V. Vce for these positions can span almost the whole +- supply, i.e. 100V so the 80V maximum of the BD140 is not enough.
Also, C1 needs to have the same orientation as C5, plus towards the base of the left BJT in the differential pair (current flows out of the base and generates positive offset in the resistors, hence + of cap to base).
Gate stoppers must be carefully considered, especially the lower one. When Vgs of the lower MOSFET reaches the zener voltage, much more current starts flowing through Q7 as now the gate is not ;infinite impedance' but rather 'zener impedance'. THe only thing that limits the current is the gate resistor. THis can be quite a lot when a low impedance load is attached and current limiting by the Vgs zener occurs at low voltages on the output of the amp! Tis is one of the more serious problems with using a BLT-MOSFET CFP.
A much more hidden problem is the zener for the top MOSFET. This may need to have diode in series (gate to source direction). Why? Consider the voltage across the Vbe multiplier. THis will be Vgs of the MOSFET for the chosen bias current, around 4V, plus one Vbe (Q7) plus bias current times 0.33 ohms (this is negligible compared to the other two terms). In all around 4.5V typically.
However, when the maximum negative current flows (through the bottom MOSFET) it flows through the 0R33 resistor, and can create such a voltage drop on this resistor that the top MOSFET zener may be forward-biassed and act as a diode, then current will flow in the negative direction falso through the gate stopper, Vbe multiplier and VAS transistor, again the current is limited only by the gate stopper of the top MOSFET. What is more, the voltage on the 0R33 resistor is limited to the voltage on the Vbe multiplier (the diode forward voltage and Vbe of Q7 cancel out). It is actually possible to use this fact as the current limit for the negative half of the output stage, simply by replacing the zener with a regular diode. However, some manipulation of zener voltages for the top half, actual MOSFETs, desired current limits and the actual value of the 0R33 resistor must be made to make the current limit approximately symmetric for both the top and bottom half of the output stage, however 0R33 also affects thermal stability and effective gm of the bottom half (*).
* There is some merit in having slightly asymmetric output voltage and current clipping when a DC protect circuit is also present, as it will switch off the load if excessive clipping or long terms current limit occurs, protecting your speaker and amp from failure. It is a 'stupid user' countermeasure, but often people are ot deliberately stupid
You have answered 1) and 2) re protecting either Q7 in the schematic or the VAS transistor - closer to the MOSFET with the gate stoppers as current limiters is better.
If there is a source resistor present, it makes the total gate to other end of source resistor better defined for a given limit current. Otherwise it's dependable on all sorts of things, most notably tolerances in MOSFET manufacture and to a far lesser extent temperature. Source resistors usable on MOSFETs like the IRFP series in order to get reasonably good current sharing are at least 0.22 ohms, or perhaps 0.15 ohms with prior MOSFET selection., so for typical currents one expects out of an amp using those MOSFETs the voltage drop across these resistors at current limit will not be trivial, in fact around the same order of magnitude as the total change from Vgs treshold to Vgs limit. This significantly reduces the influence of MOSFET tolerances, and makes for an easier choice of zeners.
Regardless, the forward biasing of a zener on one half of the push-pull output when the other half zener is conducting scenario has to be considered. In a regular complementary output this occurs whenever Vbias (gate to gate of the P and N ch part) plus one diode forward voltage is less than the zener voltage, and where appropriate a forward biassed regular diode has to be added in series with the zener or it will clamp the maximum drive voltage to the MOSFET to the bias voltage plus one forward drop. This is often not enough for a sensible limit current when source resistors are present.
Hi AKSA, pretty sure the zobel on the Q9 n-mos runs from gate to drain.
I've made a few changes and laid out a single sided board designed for through hole components. You will see a couple of ground traces running topside; however, I've added generous vias for anyone interested in etching the board and using insulated wire to connect the traces.
If someone has the time to check this that would be fantastic!
EDIT: Q5 will need a heatsink so I'll update the layout tomorrow.
I've made a few changes and laid out a single sided board designed for through hole components. You will see a couple of ground traces running topside; however, I've added generous vias for anyone interested in etching the board and using insulated wire to connect the traces.
If someone has the time to check this that would be fantastic!
EDIT: Q5 will need a heatsink so I'll update the layout tomorrow.
Attachments
you have dual N channel for a quasi output stage.
Both the drains point towards the +ve
both the snubbers are to the drains.
I think Aksa thought the lower output looked upside down because it was similar to a complementary output stage.
You added D5 to the upper protection Zener.
What is the reason for not adding a similar diode for the lower Zener?
Both the drains point towards the +ve
both the snubbers are to the drains.
I think Aksa thought the lower output looked upside down because it was similar to a complementary output stage.
You added D5 to the upper protection Zener.
What is the reason for not adding a similar diode for the lower Zener?
Last edited:
Q6 (bias servo) should actually be in thermal contact with Q7. It may well work by sensing the heatsink but this needs to be tested (at least in simulation). Also, consider that getting good hermal contact with the MOSFET relies on the back of Q6 (collector metal) being right over the crystal inside the MOSFET, so it should actually be mounted the same as the MOSFET, not at 90 deg angle.
Ilimzn,
Good input, thank you!
Since the bottom mosfet passes no gate current, the dissipation of Q7 will very little, since idle Vgs will be around 4.1V and at flat strap, at say 7A, the Vgs will increase about to 5V and while Q7 current increase, its Vce will decrease considerably as waveform passes to high negative potential. The bias generator creates a voltage across Vgs of mosfet, R18 source 0.33R, and Vbe of Q7. Essentially, the last will change little with temperature, so my argument would be to use Q6 on the heatsink. R18 will drop more volts at current flow, too, and this will tend to degeneration since the emitter of Q7 is in the loop.
Andrew,
You are correct, sleep at the wheel, thank you!
The question is: Will this elegant CFP 'quasi' (is this a quasi-quasi, or perhaps a quasi2, using Indonesian grammar?) sound better subjectively than the conventional quasi using a baxandall network on the inverting transistor?
Only an AB test will give us the answer....... thank you Ranchu, we await!
Hugh
.
Good input, thank you!
Since the bottom mosfet passes no gate current, the dissipation of Q7 will very little, since idle Vgs will be around 4.1V and at flat strap, at say 7A, the Vgs will increase about to 5V and while Q7 current increase, its Vce will decrease considerably as waveform passes to high negative potential. The bias generator creates a voltage across Vgs of mosfet, R18 source 0.33R, and Vbe of Q7. Essentially, the last will change little with temperature, so my argument would be to use Q6 on the heatsink. R18 will drop more volts at current flow, too, and this will tend to degeneration since the emitter of Q7 is in the loop.
Andrew,
You are correct, sleep at the wheel, thank you!
The question is: Will this elegant CFP 'quasi' (is this a quasi-quasi, or perhaps a quasi2, using Indonesian grammar?) sound better subjectively than the conventional quasi using a baxandall network on the inverting transistor?
Only an AB test will give us the answer....... thank you Ranchu, we await!
Hugh
.
Last edited: