In what recording or passage do you hear this? I could make a comparison with DeltaWave of previous and new PCM2DSD FW.
Up to you. In recent years I have learned the hard way to avoid making circuits with single source proprietary parts and where doing so is unavoidable making an extra plug-in module for such parts (e.g. FPGA or USB2I2S bridge) so if necessary only a small module need a redesign when the next chip shortage hit's.
It will, we have a chip glut now and MFG's will as such phase out unprofitable production lines on older processes, some parts that cannot be translated to other processes and when the process is done something will happen that will drive demand through the roof and suddenly non-core parts will be back at 104 weeks lead time and zero stock.
The second circuit in Post #2910 can be used not just to recover a full CMOS clock from a lower level one but also works to square a sinewave. Using 74AC04 it was tested with 10MHz as -102dBc @ 1Hz with the input clock itself (selected Efratom Model FRK Rubidium Frequency Standard) ast -103dBc @ 1Hz.
At 1kHz the "self biased" circuit ends up with a bit more phasenoise (-155dBc vs -158dBc) than the "fixed bias" version. The fixed bias version using NC7.... logic is used in Crystek "femto clock" canned oscillators and the main differences appears not the circuit - which seems very similar no matter which version, but the actual crystal. So it gives us at least a decent idea what potential phase noise performance of NC7.... logic is.
Anyway, I think this simple circuit will do fione.
Nope. The correct Model are two Mosfets, N/P-Channel. More precisely, the correct model for a clock buffer is this:
Unfortunately manufacturers are unlikely to provide non-encoded macro models at this level of detail and worse, in an encoded model we cannot even guess what is modelled and what not.
As remarked, when the signal is steady state, it will be equal to the N or P-Channel device saturated.
In dynamic state (when the actual edge happens - which may be what we are interested in) the impedance is poorly defined.
Seeing that current goes up as we approach crossover, it may be that at edge near mid-supply we actually have the lowest impedance.
Due to way N and P-Channel Fet's are made we can either balance capacitance between N & P or static impedance. Neither one is ideal. So there is always a problem somewhere.
Nope. The 50 Ohm termination is at the far end of the line. To what degree we get transmission line effects depend on a wide range of factors.
Slow rise time increases uncertainty around the switching point. Once we include 1LF noise from various Mosfets and ground and supply bounce ON CHIP the "randomising" factor on actual switching can become substantial.
This is why a clock squarer is not normally integrated on chip in low phase noise applications.
It cannot, using discrete logic.
In this case, probably one would use a bit switch on chip that is designed to have precisely equal resistance. Something that is sometimes seen is a trim resistor in the N-Channel source that increases the resistance statically to match the P-Channel device. However this now again messes with capacitances.
With a complete chip to design there are no doubt ways to deal with it, Marcel would be the one to ask how.
If making a discrete DAC we have a problem that is likely intractable and also likely ONE of the reasons for the rather poor measured results, even with 0.001% naked bulkfoil resistors for 10 bux a throw.
Hence the spring Audio solution of a secondary "error correction DAC" running in parallel.
There is a wide range of logic families and only certain specialised bus driver IC's for use in driving impedance controlled backplanes have controlled and equal impedance. It seems to be a little challenging to achieve.
The 74ALVC164245 I intend to use as actual bit switch seems to be equal impedance of appx 35..40 Ohm in +/- directions and thus could be included in the calculations of the Resistor values for a Kaiser (or other) window function.
Yes, naturally. In a true balanced DAC structure the effects of unequal drive impedance should wash out mostly. And using the bit-switch IC should equalise the issue.
Thor
There is a little more to say about PCM2DSD today. Previous version does have what sounds like some birdies/state-variable-settling at when a note goes to silence. Its almost like a little "rattling snare drum wires back in the other side of the recording room" type of sound. Not all PCM to DSD converters have the same quirk, but they seem to have their other problems. So PCM2SDSD is not perfect, which I think we always knew. That said, it sounds better in terms of transient-attacks, imaging, and low level music details in the previous version, as compared to the latest version. Whether or not that is solely attributable to the dither I don't know. What I do know is that the dither level of the previous version was sensitive to very small changes on the order of .01dB. Maybe dB isn't the best way to measure it however, could simply be a particular pattern of dither occurs at a very specific level.
Both transistors are in saturation in the midpoint, so the output resistance is much higher than when the output is high or low. With series termination, if the transmission line delay is larger than half the transition time, the output will be high or low again by the time the termination resistor needs to absorb the reflection.
I use the term saturation in the way analogue IC designers use it when they talk about MOSFETs: VDS > VGS - Vth (according to overly simplified strong inversion equations), MOSFET acting as an amplifying device rather than a switch. Power MOSFET designers use the exact opposite definition.
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??? I would posit the opposite is true.
Both transistors conduct at maximum, so in effect they appear for AC more or less in parallel (depends on parasitics and bypassing) the impedance is in fact lowest. We certainly see this in Transfer Gates (aka analogue switches) where impedance is lowest midpoint.
However, if instead my "inductive" reasoning is wrong and instead the impedance at midpoint is the highest, it does not change my core contention that the output impedance of a CMOS Inverter dynamically is nothing near constant, but very variable.
My main point is to highlight this, as there seems to be an assumption of a reasonably constant value.
On PCB's we often do not have traces long enough compared to the output rise time to get TL effects.
So in this case we drive a capacitive load. With a nonlinear impedance.
Thor
There should be no problem to look at these differences in DeltaWave as they should be higher than the tiny spurs which you could not hear although those were easily seen on measurement. So do you have a recording or a passage which I could use for this?
I know what you mean. However, this is basically just for a one-off clock board for testing dacs and external clocking. I'll continue to think about it though.
Yeah, I know a switch is an overly simplistic model, just like giving a nominal value of 20R is also overly simplistic. However when a nice looking square wave comes out then we don't usually worry about it too much. In this case I want to be able to drive an ill defined parallel terminated load inside a black box. Want to do the justice to the Accusilicon clocks, but they are only so good to begin with. Maybe Iancanada's new clock modules will be somewhere in between Accusilicon and Andrea Mori and or Acko clocks.
True, but we are able to do it well enough using squarers for sine wave oscillators. It may be that pulse down a line is a worse case than a sine wave simply because edges are bouncing around. For a sine wave the problem may come closer to something stub matching problem to control reflections. Also noise sensitivity is dependent on amplitude noise on the clock signal edge as well as receiver threshold noise.
Thing is, many people have found that using 100R damping resistors ends up sounding better than 33R or 27R. Back at Wadia at the end of a dac design after doing a lot of experiments and optimizing, last thing they would do is tune damping on all the lines. Whatever sounded best was what they used. Yes, clock frequencies were lower, but sometimes its a question of do you believe the meter or do you believe your ears? If you do some informal listening tests with several people sometimes you find out the ear is probably the better piece of information to guide a design choice. Depends what the dac is for. If its for listening by humans, well, you know.
Its not on chip in this case either, its on board but its a separate piece of circuitry.
Anyway, since its inside a black box if I really want to I can send a pulse down the line and see what bounces back. However, that doesn't mean the next black box is going to be the same. Maybe best to try to find a reasonable compromise or to make the series damping adjustable. Problem there is most people might not have equipment to adjust it.
Also, and to reiterate, IIUC in this case the circuit inside the black box measures as adding very little phase noise to an ultra-low phase noise sine wave clock. To accept a square wave input is sort of supported as a low-cost alternative until someone can afford a better clock.
Of course it possible to show differences between any two PCM to DSD algorithms; it can be done with two different HQ Player modulators. The question I have is how do you make sense of the differences? How do you know if one sounds better than the other? If you want to know that just listen to both on a good enough system. Its more direct and to the point.
This is absolutely true, HOWEVER the exact mechanism there is poorly understood.
Complex systems have complex problems.
If optimised for a 1V PP sinewave (which is common), you can make a divider after the Accusilicon clock. Perhaps the receiving circuit is badly overdriven?
If the clock run's at 3.3V and is more less standard cmos and the sink termination is 50 Ohm, I think 68R series and 100R to ground after a suitable driver should come close to 50 Ohm and 1V PP.
Thor
As I have said before the improvements made to PCM2DSD firmware were intended for Marcel's RTZ dac. Listening to it with another dac and making sweeping claims based on that without any real evidence is just your normal way of trying to get attention.
Yes. How else to explain his claim that latest FW sounds worse on Marcel's DAC even though he does not even have such device.
If it sounds worse on some other dac why post in this thread? This thread is not about PCM2DSD. Threadjacking is against forum rules.
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I used PCM2DSD with Acko's Marcel dac while it was here. Also, there is a Marcel dac on my bench right now in the process of assembly. No matter, while Acko's dac was here I had the opportunity to compare Andrea's dac with Marcel's at several points along the way.
Moreover, Marcel is the OP of this thread. If he finds any commentary unsuited to the subject matter of the thread I expect he will let us know.
Moreover, Marcel is the OP of this thread. If he finds any commentary unsuited to the subject matter of the thread I expect he will let us know.
Except as Marcel reminds us from time to time, its not necessarily distortion in the traditional sense. Its more likely birdies, chirps, and other weird little noises that have some correlation with a bin frequency. Thus the level of such a spur only represents an average level of correlation, not peak quirky noise. Right?
So the spurs are indications of one of the things that is changing. That's not necessarily everything that changed though. Transients don't show up well on typical FFTs because they are very dependent on phase, which is not shown in the graph of correlation-magnitude versus frequency.
Measuring transient behavior to similar accuracy requires a very different type of test. Its possible to produce more of a transient time-domain waveform by using a multi-tone test signal in the frequency domain however. But we need to look to see that phase is preserved at the output for each tone of the multitone test signal.
Or as someone else effectively summarized in another thread: we know the result of our measurements, but we are blind to anything we don't measure.
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