2stageEF high performance class AB power amp / 200W8R / 400W4R

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2stageEF 50W MOSFET - aka SA2015MT

Simulation only: 50W/8R MOSFET amplifier for mid and treble in a 3 channel active crossover power amplifier:

  • combined TMC/Cherry compensation
  • using 2x30V AC for supply
  • THD20k@50W@8R: 0.0003 %
  • overall PM 80, GM16
Simulation shows good and stable results but will it work on breadboard?

BR, Toni
 

Attachments

  • 2stageef_50w_mosfet.png
    2stageef_50w_mosfet.png
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  • 2stageEF_MOSFET_class_AB_power_amplifier_irfp240_50w.asc
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  • needed_libs.zip
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Simulation only: 50W/8R MOSFET amplifier for mid and treble in a 3 channel active crossover power amplifier:

  • combined TMC/Cherry compensation
  • using 2x30V AC for supply
  • THD20k@50W@8R: 0.0003 %
  • overall PM 80, GM16

Hi Toni

Nice to see you continue to work on this, all I have done recently is mathematics, not quite real, even if it pays real money.
How do you plan to handle the crossover?
I plan to implement it as part of the amplifier, just like a power op-amp.
A bit less flexible of course, will probably use DSP to find the frequency response then build that curve into the amp.

Best wishes
David
 
Simulation only: 50W/8R MOSFET amplifier for mid and treble in a 3 channel active crossover power amplifier:

  • combined TMC/Cherry compensation
  • using 2x30V AC for supply
  • THD20k@50W@8R: 0.0003 %
  • overall PM 80, GM16
Simulation shows good and stable results but will it work on breadboard?

BR, Toni

Hi Toni,
Nice to have you back here, very nice amp. I suggest you to bootstrapped the cascode biasing instead referenced to the ground, and you can have some THD improvement (Q19 on the attached picture). By the way I think that you need to increase the zener (D6) current to pass the knee.
BR Damir
 

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  • THD-improvement.jpg
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Hi Toni
...
How do you plan to handle the crossover?
...

Dear Dave,

the plan is to use an analog 3 channel LR24 with time delay blocks to split the input signal into 3 blocks. (for crossover have a look at Rane Corporation)
Bass speaker will get the 200W 2StageEF amp.
Mid speaker will get a 50W 2StageEF MOSFET amp.
Treble speaker will get a 50W 2StageEF MOSFET amp.
A tower case which contains the 3 amplifiers + active crossover will be placed directly left or right at the speaker.

My Denon AVR-X7200W will handle the DSP part if needed.

BR, Toni
 
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Hi Toni,
Nice to have you back here, very nice amp. I suggest you to bootstrapped the cascode biasing instead referenced to the ground, and you can have some THD improvement (Q19 on the attached picture). By the way I think that you need to increase the zener (D6) current to pass the knee.
BR Damir

Thx for the hints and the nice words!
Have incorporated your recommendations. Attached the corrected version.

BR, Toni
 

Attachments

  • 2stageef_50w_mosfet_pm_gm.png
    2stageef_50w_mosfet_pm_gm.png
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  • 2stageEF_MOSFET_class_AB_power_amplifier_irfp240_50w.asc
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  • dual_tian.plt.txt
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Attached the corrected asc to measure the inner loop as recommended by HarryDymond

BR, Toni
 

Attachments

  • needed_libs.zip
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  • 2stageEF_MOSFET_class_AB_power_amplifier_irfp240_50w.asc
    35.6 KB · Views: 84
  • 2stageef_50w_mosfet_pm_gm_corrected.png
    2stageef_50w_mosfet_pm_gm_corrected.png
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LTspice allows capacitors with value zero!

"Ctian" will be used for switching inputs to ground using 1kF cap during calculating "Tianprobe B".

BR, Toni
 

Attachments

  • 2stageef_50w_mosfet_pm_gm_using_ctian.png
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  • 2stageEF_MOSFET_class_AB_power_amplifier_irfp240_50w.asc
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  • needed_libs.zip
    9.1 KB · Views: 90
LTspice allows capacitors with value zero!

I didn't know that. When I tried 0 value resistors I received errors so I never tried capacitors.
Is that new? Will try to check it today but my LTSpice machine is down, needs to be fixed first.
So I haven't had a chance to check your latest.
The ULGF is pushed pretty far up and PM is not conservative, to say the least. I assume you have checked this as the output transistors approach the rails. You think this is adequate?

Best wishes
David
 
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...
The ULGF is pushed pretty far up and PM is not conservative, to say the least. I assume you have checked this as the output transistors approach the rails. You think this is adequate?

Best wishes
David

Dear David,

thanks for checking this. Any recommendations are always highly welcome. As it is a work in progress I have it pushed to the limits watching for instabilities (e.g. square wave overshoot, oscillation ...).

The initial question was
"... but will it work on breadboard?"
caused by the "not so good" cherry compensation test results during development of this threads amplifier. Maybe this combined compensation type will not work as expected.

My holidays will start in 9 days - hopefully I will find time building a prototype.;)

BR, Toni
 
The ULGF is pushed pretty far up and PM is not conservative, to say the least.

Phase margin of the global loop looks to be over 60°. This should be plenty, no?

The phase margin of the inner loop is much smaller, perhaps you are referring to this? In my experience it can be difficult to get the phase margin much bigger without severely compromising the global loop. I’ve never investigated the sensitivity of the inner loop to component and operating variations so I don’t know if one can get away with these small margins.
 
The initial question was "... but will it work on breadboard?"
caused by the "not so good" cherry compensation test results during development of this threads amplifier. Maybe this combined compensation type will not work as expected.

This type of combined compensation is difficult to analyse.
I will be very interested in your results to see how they compare to theory.

Phase margin of the global loop looks to be over 60°. This should be plenty, no?

Maybe. I was almost shocked to see how much PM was reduced once I included a bit of capacitance in the load and simulated near peak amplitude, to reduce the output transistor Vce.
That was in my own BJT test amp, Paul made similar comments after I recommended he try such tests on his similar, BJT amp.
Not sure how it will work out here.

...of the inner loop is much smaller... In my experience it can be difficult to get the phase margin much bigger without severely compromising the global loop. I’ve never investigated the sensitivity of the inner loop to component and operating variations so I don’t know if one can get away with these small margins.
Yes, the inner loop looks a bit scary to me.
40 MHz so parasitics will matter, and not much room for error.

Best wishes
David

PS I posted a little on the problem of simultaneous optimization of the two loops, not easy but possible.
 
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...
Maybe. I was almost shocked to see how much PM was reduced once I included a bit of capacitance in the load and simulated near peak amplitude, to reduce the output transistor Vce.
...
A hint how to do this? :)

...
PS I posted a little on the problem of simultaneous optimization of the two loops, not easy but possible.

Maybe you can add a link to this? Thx!;)

BR, Toni
 
Added capacitive loads:

A1: 4.7nF || 8R
A2: 100nF || 8R
A3: 470nF || 8R
A4: 2µF || 8R

Could you clarify, as it is not visible in the screenshot - presumably the amplifier has a zobel (RC) on its output to ground, and then a series L (possibly with a parallel R) before the actual output terminal, and it is the actual output terminal at which these load networks are being connected?
 
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Could you clarify, as it is not visible in the screenshot - presumably the amplifier has a zobel (RC) on its output to ground, and then a series L (possibly with a parallel R) before the actual output terminal, and it is the actual output terminal at which these load networks are being connected?

Attached after output zobel. Have a look at the previously attached asc file.

BR, Toni
 
Attached after output zobel. Have a look at the previously attached asc file.
Looks like the Zobel isolates the amp pretty well, just like it is intended to.
Output Zobel is the R+C from output to ground.

The Thiele Network has both and R+C to ground and an L||R in series before the speaker terminals.

Are either of your referring to the L||R part of the Thiele Network?