I opened a thread here
http://www.diyaudio.com/forums/showthread.php?s=&postid=1335189#post1335189
to discuss yet another way to control a MOSFET output stage with two N-channel output devices, using a very simple local NFB loop to improve linearity.
Alex
http://www.diyaudio.com/forums/showthread.php?s=&postid=1335189#post1335189
to discuss yet another way to control a MOSFET output stage with two N-channel output devices, using a very simple local NFB loop to improve linearity.
Alex
expert review requested
In the thread on LME49810 an EE student asked for design advices to make a LME49810 based power amplifier.
Beeing in the process of doing it myself I described for him my approach that I am copying hereunder
I would like to have your comments on this if you have the time.
"
Let me give you a few tips as they come out of my head.
For what you are saying ( EE students), the design around LME49810 is a great choice. You can concentrate on the main aspect of power amplifiers: the output stage.
This is not a trivial task.
I would first evaluate the constraints.
If possible I would avoid the packaging constraints by making the device a large open frame with for example a plexiglas protection plate.
This will allow you to reach without constraints:
optimal cooling, optimal LF magnetic shielding ( by distance and orientation of transformer).
Then I would start from the heatsink. If money permits, Fisher elektronic makes great extruded compact forced air cooled heatsinks with machined faces to allow good thermal contacts. The heatsink is a rectangular block with integrated ventilator and two opposit mounting faces for the power transistors. Very good theta ( 0.1°/watt). You can mount the pcb's with the LM on the other 2 sides, one per channel.
Then I would estimate the power dissipated by the output transistors on a reactive load of 45°.
A good rule of thumb is : average power dissipated in transistors = 60% of power delivered. Another good rule is keep average T° of heatsink lower than 70°C or better 60°C.
Then You have to make the choice of output transistors and their number in parallel. I would use BGT's from Onsemi ( thermaltrack with diode integrated)
Then you need to estimated the +-Vcc's and the SOA aspect's related to output protection and number of transistors. and peak power in reactive load
The Vcc is an estimate because voltage drops at full power (so clipping) depends on a lot of unknows: ac dips, transformer efficiency, rectifier and fuses voltage drops, capacitor filtering sizes and output headroom at full power before clipping transistors. Because it is an internal project and because of LME flexibility I would start for your 150w/4ohms with a 45Volts dc. Yes this is a lot more than the simple calculation of : average power ( 150W) = Vcc^2/2R ( Vcc is peak amplitude!!!).
Now that Vcc is estimated you can find the voltage of the ac transformer ( see some rule of tumbs on toroidal transformer vendors site like powertronix). Tweaking later can be done by adding or removing some turns on the power transformer with enameled pair of wires of right AGW.
Now you need to estimate the VA rating of the transformer. A good rule of thumb is minimum twice the delivered average power. In this case 300VA or more if money permits.
Now you need to estimate the peak power and peak current in load therefore in output transistor. This will allow you to estimate the type and number of output transistors in //. In your case I would guess 4NPN's and 4PNP's (NJL 3281, 1302).
Peak power dissipated on reactive load can be a lot more than on resistive. A good estimate would be: take a worse case minimum load impedance module ( of complex impedance) half of the rated 4 ohms and a worse case of 45° phase shift that the load could present at a certain frequency. These are estimates because music is transient ( see Benjamin in the AES papers for a good overview). Estimate the current per single transistor ( divide by the number of transistors)
With this load, draw on the SOA spec the elliptic load line and see how many transistors you need to accomodate a non crossing of the SOA curve ( you will be surprise). If necessary, put more transistors.
Do not forget to derate the curve at maximum case temperature that you can now estimated ( if your heatsink remains at 60°C worse case) knowing the peak power per transistor and the theta of case to heatsink ( about 1°c/watt if very good mounting).
This procees requires some interation.
You are now able to design a good non intrusive SOA protection device ( see Leach papers and book or very good paper from Mikek diy member.
You still need to estimate a minimum capacitor filtering size. Some rule of thumb is 2 joules of power stored per 10 watt ouput power. Energy = Vcc^2 C/2 joules
Now you need a topology and to tune the biasing of your output transistors. I would suggest to use the triple output stage ( Locanthi) that is well described by Leach. The first emitter follower of this triple stage is the output transistor of the LME.
Use a 0.1 ohm or 0.15 ohm in each emitter of the output transistors. They help in thermal stability ( thermal runaway avoidance) and current equilisation in // transistors). These are power resistors !!! With 4 ohm load try to match the ouput transistors for beta if you can or use same batch from supplier and then go for 0.1 ohm. This will give you better crossover distortion in case of optimal biasing but weaker thermal stability.
Very good heatsink and thermaltrack helps there but you must try. With the resistance chosen, ajust optimal bias current in output transistors for minimal crossover distortion: this is gmRe =1 where Re is emitter resistor and gm is transconductance of output transistor. this is equal to IcRe=Vt=26mV, so ajust current ( Vbe multiplier or thermaltrack diodes with some potentiometer) until V on Re is 26mV
This is theoretical because Re should include the internal resistance of the transistor + Rb/Hfe where Rb is the resistance in the base divided by Hfe of transistor. On top of that the 26mV is Vt = kt/q which is temp dependant.
The best is to allow the transistor to reach average operating temperature and bias then for minimum distortion using a spectrum analyzer. The formula gives you a good approach.
Your SOA protection device is also a short circuit protection. An handy way of using it is to activate the mute pin of LME via optocoupler and some delay before restart.
You need perhaps a DC servo to avoid using coupling capacitors and a DC protection that activates an ouput relay to protect your speakers in case of power transistor failure or any other in the signal chain. A good DC protection circuit can be found in SELF's book. I would switch the relay with an optocoupler.
The relay contacts should be well investigated for no distortion.
Even then contact protection is mandatory. Because you will switch a reactive load , spikes are generated. The usual two clamping diodes seen in // with collector emitter or output transistors should be placed after the contact( speaker side) between +Vcc/ speaker ouput and -Vcc speaker output. This will clamp the surge to VCC. Now you know that the worse case voltage on the contacts will be less than 300V wich is the start of glow arcing.
You are still left with metallic arc discharge on your contact. A good rule is that the voltage gradient ( dV/dt) between contacts remains under 1V/microsecond to avoid this arc. Using a large bipolar capacitor as contact protection in // with them will do it. C dV/dt=I peak load. Then, C greater than I load /1.000.000 so for 100A peak C> 100microF !!
With this capacitor you still need to protect the contatcts when closing them. This is usually done via a resistor in serie with Cbut this resistor has a detrimental effect on opening because a voltage equal to R times I peak will be present and arcing will happen at the begining.. In the particular case of switching speakers we can switch speakers on with mute of LME still engaged therefore there is no voltage on the contacts on closing and they will never be degraded. This is very important and overlooked or avoided by not using relays.
Finally, you get a state of the art amplifier !!
A final hint/ I would use BJT's because of very accurate model made by Andy_c , diy member for onsemi thermaltrack's. Then your guys should then play with LTspice and estimate operation of the amplifier. They will be able to show and use their theoretical knowlege before learning practical through this excellent project ( ... continued on next message)
JP
In the thread on LME49810 an EE student asked for design advices to make a LME49810 based power amplifier.
Beeing in the process of doing it myself I described for him my approach that I am copying hereunder
I would like to have your comments on this if you have the time.
"
Let me give you a few tips as they come out of my head.
For what you are saying ( EE students), the design around LME49810 is a great choice. You can concentrate on the main aspect of power amplifiers: the output stage.
This is not a trivial task.
I would first evaluate the constraints.
If possible I would avoid the packaging constraints by making the device a large open frame with for example a plexiglas protection plate.
This will allow you to reach without constraints:
optimal cooling, optimal LF magnetic shielding ( by distance and orientation of transformer).
Then I would start from the heatsink. If money permits, Fisher elektronic makes great extruded compact forced air cooled heatsinks with machined faces to allow good thermal contacts. The heatsink is a rectangular block with integrated ventilator and two opposit mounting faces for the power transistors. Very good theta ( 0.1°/watt). You can mount the pcb's with the LM on the other 2 sides, one per channel.
Then I would estimate the power dissipated by the output transistors on a reactive load of 45°.
A good rule of thumb is : average power dissipated in transistors = 60% of power delivered. Another good rule is keep average T° of heatsink lower than 70°C or better 60°C.
Then You have to make the choice of output transistors and their number in parallel. I would use BGT's from Onsemi ( thermaltrack with diode integrated)
Then you need to estimated the +-Vcc's and the SOA aspect's related to output protection and number of transistors. and peak power in reactive load
The Vcc is an estimate because voltage drops at full power (so clipping) depends on a lot of unknows: ac dips, transformer efficiency, rectifier and fuses voltage drops, capacitor filtering sizes and output headroom at full power before clipping transistors. Because it is an internal project and because of LME flexibility I would start for your 150w/4ohms with a 45Volts dc. Yes this is a lot more than the simple calculation of : average power ( 150W) = Vcc^2/2R ( Vcc is peak amplitude!!!).
Now that Vcc is estimated you can find the voltage of the ac transformer ( see some rule of tumbs on toroidal transformer vendors site like powertronix). Tweaking later can be done by adding or removing some turns on the power transformer with enameled pair of wires of right AGW.
Now you need to estimate the VA rating of the transformer. A good rule of thumb is minimum twice the delivered average power. In this case 300VA or more if money permits.
Now you need to estimate the peak power and peak current in load therefore in output transistor. This will allow you to estimate the type and number of output transistors in //. In your case I would guess 4NPN's and 4PNP's (NJL 3281, 1302).
Peak power dissipated on reactive load can be a lot more than on resistive. A good estimate would be: take a worse case minimum load impedance module ( of complex impedance) half of the rated 4 ohms and a worse case of 45° phase shift that the load could present at a certain frequency. These are estimates because music is transient ( see Benjamin in the AES papers for a good overview). Estimate the current per single transistor ( divide by the number of transistors)
With this load, draw on the SOA spec the elliptic load line and see how many transistors you need to accomodate a non crossing of the SOA curve ( you will be surprise). If necessary, put more transistors.
Do not forget to derate the curve at maximum case temperature that you can now estimated ( if your heatsink remains at 60°C worse case) knowing the peak power per transistor and the theta of case to heatsink ( about 1°c/watt if very good mounting).
This procees requires some interation.
You are now able to design a good non intrusive SOA protection device ( see Leach papers and book or very good paper from Mikek diy member.
You still need to estimate a minimum capacitor filtering size. Some rule of thumb is 2 joules of power stored per 10 watt ouput power. Energy = Vcc^2 C/2 joules
Now you need a topology and to tune the biasing of your output transistors. I would suggest to use the triple output stage ( Locanthi) that is well described by Leach. The first emitter follower of this triple stage is the output transistor of the LME.
Use a 0.1 ohm or 0.15 ohm in each emitter of the output transistors. They help in thermal stability ( thermal runaway avoidance) and current equilisation in // transistors). These are power resistors !!! With 4 ohm load try to match the ouput transistors for beta if you can or use same batch from supplier and then go for 0.1 ohm. This will give you better crossover distortion in case of optimal biasing but weaker thermal stability.
Very good heatsink and thermaltrack helps there but you must try. With the resistance chosen, ajust optimal bias current in output transistors for minimal crossover distortion: this is gmRe =1 where Re is emitter resistor and gm is transconductance of output transistor. this is equal to IcRe=Vt=26mV, so ajust current ( Vbe multiplier or thermaltrack diodes with some potentiometer) until V on Re is 26mV
This is theoretical because Re should include the internal resistance of the transistor + Rb/Hfe where Rb is the resistance in the base divided by Hfe of transistor. On top of that the 26mV is Vt = kt/q which is temp dependant.
The best is to allow the transistor to reach average operating temperature and bias then for minimum distortion using a spectrum analyzer. The formula gives you a good approach.
Your SOA protection device is also a short circuit protection. An handy way of using it is to activate the mute pin of LME via optocoupler and some delay before restart.
You need perhaps a DC servo to avoid using coupling capacitors and a DC protection that activates an ouput relay to protect your speakers in case of power transistor failure or any other in the signal chain. A good DC protection circuit can be found in SELF's book. I would switch the relay with an optocoupler.
The relay contacts should be well investigated for no distortion.
Even then contact protection is mandatory. Because you will switch a reactive load , spikes are generated. The usual two clamping diodes seen in // with collector emitter or output transistors should be placed after the contact( speaker side) between +Vcc/ speaker ouput and -Vcc speaker output. This will clamp the surge to VCC. Now you know that the worse case voltage on the contacts will be less than 300V wich is the start of glow arcing.
You are still left with metallic arc discharge on your contact. A good rule is that the voltage gradient ( dV/dt) between contacts remains under 1V/microsecond to avoid this arc. Using a large bipolar capacitor as contact protection in // with them will do it. C dV/dt=I peak load. Then, C greater than I load /1.000.000 so for 100A peak C> 100microF !!
With this capacitor you still need to protect the contatcts when closing them. This is usually done via a resistor in serie with Cbut this resistor has a detrimental effect on opening because a voltage equal to R times I peak will be present and arcing will happen at the begining.. In the particular case of switching speakers we can switch speakers on with mute of LME still engaged therefore there is no voltage on the contacts on closing and they will never be degraded. This is very important and overlooked or avoided by not using relays.
Finally, you get a state of the art amplifier !!
A final hint/ I would use BJT's because of very accurate model made by Andy_c , diy member for onsemi thermaltrack's. Then your guys should then play with LTspice and estimate operation of the amplifier. They will be able to show and use their theoretical knowlege before learning practical through this excellent project ( ... continued on next message)
JP
next part on grounding and layout
To be complete, some practical tips on layout and grounding.
You should avoid problems (coupling) within the amplifier and coupling from outside.
The rules to follow are :
1 understand where currents are flowing,
then minimize the size of the loop formed by a current and its return current. The return current will follow the path of least impedance (not least resistance) towards its origin . Therefore many currents will follow the path of minimum loop ( minimum inductance) and then radiate or pick up less (mutual magnetic coupling) in/from other loops. Try to minimize these loops by layout. This is very important for the loop made from postive current flowing from decoupling cap power supply at output transistor level to NPN power transistor to load and back to ground of decoupling cap. This current has a lot of high frequencies and this loop should be minimized and twisted. The same for the negative part.
2 Use a single point grounding at audio frequencies per group of currents : one group for load output currents and decoupling caps at power transistor level, one group for low level audio ( currents for the LME and its decoupling caps.
Single point grounding means each current has its own return to ground point and back to origin.
3 put a small resistance between Vcc of power transistors and Vcc's decoupling caps of LME. This will force the currents to stay in their original loops. This will avoid ground loop coupling.
4 connect each ground to main power supply smoothing caps central point. This point should be individually connected to the central tap of transformer and to the chassis safety ground. A small ( one ohm) resistance can be put in the ground connection coming from the ouput transistors ground point. The usefulness of this resistor should be tested by measurements. Ac noise filters should be connected to the chassis at the entrance.
5 make a clean ground piece (large isolated pcb strip) where the external shield of of incoming signal and input filtering caps should be connected at the entrance. This clean ground way not carry internal currents and should be connected with a strip to the chassis safety ground. This connection will divert any external ground loop currents or shield picked up noise from entering the circuit. Use a shielded twisted pair to bring in the audio with shield connected to the clean ground ( not audio ground) just described and at the entrance . This ground strip can run along the frame close to the output leads and receive the rfi outpout lead capacitor filters to avoid HF rectification through speaker pairs.
two more tips:
avoid proximity of ground to feedback node of LME (- INPUT). This would create a parasitic capacitance with oscillation problems.
Be carefull with the layout of the feedback resistor. The current comes from the LME output transistor, flows in the bases of the emitter followers to the next one, through the power resistors and then back via the feedback resistor. This loop should be minimized and the connection of the feedback resistor track to the output should be after the connection point of the power resistors.
Cheers
JP
To be complete, some practical tips on layout and grounding.
You should avoid problems (coupling) within the amplifier and coupling from outside.
The rules to follow are :
1 understand where currents are flowing,
then minimize the size of the loop formed by a current and its return current. The return current will follow the path of least impedance (not least resistance) towards its origin . Therefore many currents will follow the path of minimum loop ( minimum inductance) and then radiate or pick up less (mutual magnetic coupling) in/from other loops. Try to minimize these loops by layout. This is very important for the loop made from postive current flowing from decoupling cap power supply at output transistor level to NPN power transistor to load and back to ground of decoupling cap. This current has a lot of high frequencies and this loop should be minimized and twisted. The same for the negative part.
2 Use a single point grounding at audio frequencies per group of currents : one group for load output currents and decoupling caps at power transistor level, one group for low level audio ( currents for the LME and its decoupling caps.
Single point grounding means each current has its own return to ground point and back to origin.
3 put a small resistance between Vcc of power transistors and Vcc's decoupling caps of LME. This will force the currents to stay in their original loops. This will avoid ground loop coupling.
4 connect each ground to main power supply smoothing caps central point. This point should be individually connected to the central tap of transformer and to the chassis safety ground. A small ( one ohm) resistance can be put in the ground connection coming from the ouput transistors ground point. The usefulness of this resistor should be tested by measurements. Ac noise filters should be connected to the chassis at the entrance.
5 make a clean ground piece (large isolated pcb strip) where the external shield of of incoming signal and input filtering caps should be connected at the entrance. This clean ground way not carry internal currents and should be connected with a strip to the chassis safety ground. This connection will divert any external ground loop currents or shield picked up noise from entering the circuit. Use a shielded twisted pair to bring in the audio with shield connected to the clean ground ( not audio ground) just described and at the entrance . This ground strip can run along the frame close to the output leads and receive the rfi outpout lead capacitor filters to avoid HF rectification through speaker pairs.
two more tips:
avoid proximity of ground to feedback node of LME (- INPUT). This would create a parasitic capacitance with oscillation problems.
Be carefull with the layout of the feedback resistor. The current comes from the LME output transistor, flows in the bases of the emitter followers to the next one, through the power resistors and then back via the feedback resistor. This loop should be minimized and the connection of the feedback resistor track to the output should be after the connection point of the power resistors.
Cheers
JP
JPV,
This is a really excellent and complete summary you have presented here. Its value and relevance obviously goes well beyond the application of the National driver part. There are good reminers here for all of us. Thanks for posting this.
I have only one thing that I would possibly recommend differently. Especially for a beginner, I'd go more conservative on the thermal stability by recommending to at least start out with 0.22 ohm emitter resistors in the output stage.
Cheers,
Bob
This is a really excellent and complete summary you have presented here. Its value and relevance obviously goes well beyond the application of the National driver part. There are good reminers here for all of us. Thanks for posting this.
I have only one thing that I would possibly recommend differently. Especially for a beginner, I'd go more conservative on the thermal stability by recommending to at least start out with 0.22 ohm emitter resistors in the output stage.
Cheers,
Bob
A few days ago i start to read this interesting topic.
I am interested at the speed of transistor.
In class AB amplifier is necessary to fast turn off bjt.
Toff = Tstg + Tf (storage time + fall time)
What is the maximum storage time required for audio application?
is tstg proportional to Ic? Vce? Ib?
I have read a npn bjt datasheet with tstg=15us rated at Ib = -9A
if the base charge is removed by resistor connected betwin base and emitter, can i determine tstg?
Thanks
I am interested at the speed of transistor.
In class AB amplifier is necessary to fast turn off bjt.
Toff = Tstg + Tf (storage time + fall time)
What is the maximum storage time required for audio application?
is tstg proportional to Ic? Vce? Ib?
I have read a npn bjt datasheet with tstg=15us rated at Ib = -9A
if the base charge is removed by resistor connected betwin base and emitter, can i determine tstg?
Thanks
dadouzzu said:
Usually storage time is associated with saturated switching applications. For Class AB output stages the switching time at crossover is very important, but usually the output transistor speed for an audio amplifier is characterized in terms of ft of the devices. In the early days, one was lucky to get an ft of 1 MHz or so. Later complementary devices, and many that are used to this day, have ft on the order of 4 MHz. More advanced devices, like Ring Emitter Transistors (RET) have ft in the range of 30 MHz to 60 MHz. Finally, the effective ft of vertical power MOSFETs often lies in the range of 100-400 MHz.
When output devices do not shut off quickly enough when transitioning through the Class AB crossover region, this gives rise to cross-conduction and so-called dynamic or secondary crossover distortion.
It is always desirable to have adequate turn-off current available to the base of output transistors, such as by a resistor as you mention. The more the better, but of course this impacts driver dissipation. I usually like to have at least 30 mA of turn-off current available per output device, although it is not necessarily a simple linear relationship as number of output devices is increased.
Hope this helps,
Bob
dadouzzu said:
I think you are comparing apples with oranges. The units are completely different for thermal resistance of the material (W/m-K) versus the thermal impedance of a specific pad for an output transistor (K-in^2/W).
Take a look at the following data sheet:
http://www.bergquistcompany.com/objects/data_sheets/PDS_SP_A1500_0307E.pdf
Bergquist makes a lot of good products.
Charles Hansen said:
http://www.bergquistcompany.com/objects/data_sheets/PDS_SP_A1500_0307E.pdf
that is the catalog that i had already see:
You can see that TO220 pakage at 50psi have 2.2°C/W
dadouzzu said:
The thermal impedance as CH Hansen is saying is the thermal resistance of 1 square inch of material. If the surface of your device is smaller then the thermal resistance is larger in the same proportion if same mounting
Your value is for a to220, mine is for a thermal track package which is about 80% of 1 square inch.
Jean-Pierre
The Importance of current slew rate capability
An earlier post raised a question about the importance of the speed of the output transistors in a Class-AB output stage. I thought that I would elaborate on that here,
plugging in some real numbers.
Output transistor speed is most important in connection with crossover distortion and the rate at which net output current can change. Just as with voltage, there is current slew rate. An amplifier whose output stage is incapable of adequate current slew rate will produce large amounts of crossover distortion at high frequencies and in some cases may overheat or destruct when one side of the output stage does not shut off fast enough. In the latter case, “totem-pole” or “shoot-through” or “common-mode” conduction will occur as the upper and lower parts of the output stage fight each other as the signal goes through the zero-current transition.
To put things in perspective, note that a 100-Watt amplifier produces 40V peak. At 20 kHz, this corresponds to a voltage slew rate of 5 V/us going through crossover. When driving a 4 ohm resistive load (for 200 W), this results in a current slew rate of 1.2 Amps/us.
Whether the device is a BJT or a MOSFET, the rate at which it can reduce its conducting current as it goes through crossover depends on the available base or gate discharge current in combination with the device input capacitance. This establishes the voltage rate of change at the base or gate. That voltage change, times the transconductance of the device, determines the turn-off current slew rate.
For a BJT, we have Cpi = gm/(2 * pi * ft).
For a respectable 4 MHz power BJT biased at 150 mA at idle, Cpi = 0.24 uF.
The rate of voltage change at the base, dVbe/dt = Ib/Cpi, where Ib is the base discharge current.
We then have the collector current slew rate dIc/dt as dVbe/dt * gm = 2 * pi * ft * Ib.
Notice that Ic and gm are not in this simple equation.
For a good conventional power transistor with ft = 4 MHz and a healthy Ib = 50 mA, we only get an achievable current slew rate of 1.2 Amps/us. Since a push-pull Class-AB output stage is assumed, we also have the opposite transistor that is turning on contributing to the total output current slew rate. So it is arguable that the transistor turning off only needs to be turning off at a rate of about 0.6 A/us in order to achieve the total current rate of change of 1.2 A/us demanded by 40V peak at 20 kHz into a 4-ohm load.
Of course, at crossover the collector currents are supposed to be on the order of the idle bias amount, which may be about 100 – 150 mA. Due to low-current ft droop in BJT’s, it is unlikely that the devices actually have a 4 MHz ft under these conditions. In any case, one can see that we are cutting it close are there is likely to be considerable nonlinearity under these very dynamic conditions involving high rates of change of current.
The situation is better for BJT RETs, such as the OnSemi ThermalTrak devices. Even at an idle bias current of 150 mA, these devices still manage a respectable ft on the order of 20 MHz. This means that with a base discharge current of 50 mA, each device is capable of turning off at a rate of about 6 Amps/us.
Finally, lets take a look at vertical power MOSFETs. These devices are very good in the important area of speed of current change. That is one reason why they are popular in switching power supplies.
The effective ft of a MOSFET is approximately ft = gm/(2 * pi * Ciss)
In the crossover region with an Idle bias of 150 mA, gm for an IRFP240 will be about 0.75 S and Ciss will be about 1200 pF. This works out to an ft of about 100 MHz.
Let’s see what the maximum current rate of change is for the same 50 mA gate discharge current assumed for the BJT:
Plugging in dId/dt = 2 * pi * ft * Ig, we get 32 Amps/us.
This is significantly better than even the RET BJT devices.
In a Class-AB push pull arrangement, the maximum available rate of change for the stage will be about double this, or about 64 Amps/us.
Although their lower transconductance for a given current tends to cause MOSFETs to have higher static crossover distortion that BJTs at a given output stage idle current (unless something like error correction is applied to the MOSFETs), their higher speed in regard to current rate of change allows them to produce far less dynamic crossover distortion at high frequencies.
Cheers,
Bob
An earlier post raised a question about the importance of the speed of the output transistors in a Class-AB output stage. I thought that I would elaborate on that here,
plugging in some real numbers.
Output transistor speed is most important in connection with crossover distortion and the rate at which net output current can change. Just as with voltage, there is current slew rate. An amplifier whose output stage is incapable of adequate current slew rate will produce large amounts of crossover distortion at high frequencies and in some cases may overheat or destruct when one side of the output stage does not shut off fast enough. In the latter case, “totem-pole” or “shoot-through” or “common-mode” conduction will occur as the upper and lower parts of the output stage fight each other as the signal goes through the zero-current transition.
To put things in perspective, note that a 100-Watt amplifier produces 40V peak. At 20 kHz, this corresponds to a voltage slew rate of 5 V/us going through crossover. When driving a 4 ohm resistive load (for 200 W), this results in a current slew rate of 1.2 Amps/us.
Whether the device is a BJT or a MOSFET, the rate at which it can reduce its conducting current as it goes through crossover depends on the available base or gate discharge current in combination with the device input capacitance. This establishes the voltage rate of change at the base or gate. That voltage change, times the transconductance of the device, determines the turn-off current slew rate.
For a BJT, we have Cpi = gm/(2 * pi * ft).
For a respectable 4 MHz power BJT biased at 150 mA at idle, Cpi = 0.24 uF.
The rate of voltage change at the base, dVbe/dt = Ib/Cpi, where Ib is the base discharge current.
We then have the collector current slew rate dIc/dt as dVbe/dt * gm = 2 * pi * ft * Ib.
Notice that Ic and gm are not in this simple equation.
For a good conventional power transistor with ft = 4 MHz and a healthy Ib = 50 mA, we only get an achievable current slew rate of 1.2 Amps/us. Since a push-pull Class-AB output stage is assumed, we also have the opposite transistor that is turning on contributing to the total output current slew rate. So it is arguable that the transistor turning off only needs to be turning off at a rate of about 0.6 A/us in order to achieve the total current rate of change of 1.2 A/us demanded by 40V peak at 20 kHz into a 4-ohm load.
Of course, at crossover the collector currents are supposed to be on the order of the idle bias amount, which may be about 100 – 150 mA. Due to low-current ft droop in BJT’s, it is unlikely that the devices actually have a 4 MHz ft under these conditions. In any case, one can see that we are cutting it close are there is likely to be considerable nonlinearity under these very dynamic conditions involving high rates of change of current.
The situation is better for BJT RETs, such as the OnSemi ThermalTrak devices. Even at an idle bias current of 150 mA, these devices still manage a respectable ft on the order of 20 MHz. This means that with a base discharge current of 50 mA, each device is capable of turning off at a rate of about 6 Amps/us.
Finally, lets take a look at vertical power MOSFETs. These devices are very good in the important area of speed of current change. That is one reason why they are popular in switching power supplies.
The effective ft of a MOSFET is approximately ft = gm/(2 * pi * Ciss)
In the crossover region with an Idle bias of 150 mA, gm for an IRFP240 will be about 0.75 S and Ciss will be about 1200 pF. This works out to an ft of about 100 MHz.
Let’s see what the maximum current rate of change is for the same 50 mA gate discharge current assumed for the BJT:
Plugging in dId/dt = 2 * pi * ft * Ig, we get 32 Amps/us.
This is significantly better than even the RET BJT devices.
In a Class-AB push pull arrangement, the maximum available rate of change for the stage will be about double this, or about 64 Amps/us.
Although their lower transconductance for a given current tends to cause MOSFETs to have higher static crossover distortion that BJTs at a given output stage idle current (unless something like error correction is applied to the MOSFETs), their higher speed in regard to current rate of change allows them to produce far less dynamic crossover distortion at high frequencies.
Cheers,
Bob
Wavebourn wrote something very interesting :
What is wrong with emitor follower with complex load (speaker?) and not biased into classA?
http://www.diyaudio.com/forums/showthread.php?postid=1384822#post1384822
What is wrong with emitor follower with complex load (speaker?) and not biased into classA?
lumanauw said:
I don't think that there is anything wrong with a Class-AB push-pull emitter follower driving a complex load as long as proper attention is paid to detail. This includes minimization of crossover distortion under all reasonable signal conditions, and avoidance of instability under all reasonable complex loads over all voltage and current swings.
Cheers,
Bpb
Re: The Importance of current slew rate capability
Hello Bob,
A most interesting post for me at least!. I just wonder if you can plug figures for vertical FETs in common source mode.
I have read that common emitter is slower than emitter follower (by a factor of 3 by some sources on here) with BJT's but they have huge base charge compared with MOSFETs and come out of clipping slower. Also the EF arrangement can have a base charge suckout cap or cross coupling to speed it up.
Is this the case Ft wise with mosfets (and I don't just mean power types) ?
Another person said that mosfets do not know what method of operation they are in. Anyway, I guess it's capacitance related with mosfets and I don't think common source benefits from the bootstrap effect of the source follower.
Basically I would be interested in getting an approx idea what drive current to use to drive a IRFP240 in common source (for the sake of comparison) as an example and with good speed compared with your example above.
One nifty thing with common source/emitter stages is the voltage slew rate is multiplied by the voltage gain. ie. 15V/us opamp + 6.5 times voltage gain to the rail etc could get over 100V/us.
Your mentioning of current slew rate was an enlightening point to me.
Help appreciatted.
Kevin
Bob Cordell said:
Hello Bob,
A most interesting post for me at least!. I just wonder if you can plug figures for vertical FETs in common source mode.
I have read that common emitter is slower than emitter follower (by a factor of 3 by some sources on here) with BJT's but they have huge base charge compared with MOSFETs and come out of clipping slower. Also the EF arrangement can have a base charge suckout cap or cross coupling to speed it up.
Is this the case Ft wise with mosfets (and I don't just mean power types) ?
Another person said that mosfets do not know what method of operation they are in. Anyway, I guess it's capacitance related with mosfets and I don't think common source benefits from the bootstrap effect of the source follower.
Basically I would be interested in getting an approx idea what drive current to use to drive a IRFP240 in common source (for the sake of comparison) as an example and with good speed compared with your example above.
One nifty thing with common source/emitter stages is the voltage slew rate is multiplied by the voltage gain. ie. 15V/us opamp + 6.5 times voltage gain to the rail etc could get over 100V/us.
Your mentioning of current slew rate was an enlightening point to me.
Help appreciatted.
Kevin