Edmond Stuart said:
Hello Edmond,
Thanks for the reply, but this was not really the question I asked. I was interested in the Ft (GBP) in common source mode and _current_ slew rate for designing.
What it is, is I am working on a LDO regulator for the output stage and I can get good voltage slew rates but it looks like hefty gate currents will still be required compared with runnng it in source follower mode. In fact maybe more so.
So I am wondering whether to just go source follower though I don't think it can give the pulse drain current output of common source....
This also has consequences for BJT-Mosfet CFP output stages also.
Thanks for the replies guys.
Kevin
Re: Re: The Importance of current slew rate capability
Hi Kevin,
I have never made a MOSFET power amplifier using the common source mode, but I believe some have done so quite successfully.
The key thing to remember, in my opinion, is that in common source the Cgd is Miller-multiplied. This can have different effects on speed depending on how you look at it.
With regard to gate drive current, keep in mind that in either configuration you have to swing the full signal voltage across Cgd and you have to swing the full output-current-related voltage across Cgs.
So there are two charge-discharge mechanisms at work, one more related to output voltage rate of change, the other more related to output current rate of change. The amount of current that your driver can source and sink to the gate ideally covers both of these even if they occur simultaneously.
Finally bear in mind that Cgs is fairly constant, while Cgd can change by a very large amount as Vds gets small. If you want to run the output stage to within, say less than 5V of the rails, and you want to maintain a high slew rate capability under those conditions, you really need to look out for large Cgd.
Your amplifier stability evaluation, both for global and local stability, must also take account of large values of Cgd that come into play as you approach the rails.
Cheers,
Bob
Fanuc said:
Hi Kevin,
I have never made a MOSFET power amplifier using the common source mode, but I believe some have done so quite successfully.
The key thing to remember, in my opinion, is that in common source the Cgd is Miller-multiplied. This can have different effects on speed depending on how you look at it.
With regard to gate drive current, keep in mind that in either configuration you have to swing the full signal voltage across Cgd and you have to swing the full output-current-related voltage across Cgs.
So there are two charge-discharge mechanisms at work, one more related to output voltage rate of change, the other more related to output current rate of change. The amount of current that your driver can source and sink to the gate ideally covers both of these even if they occur simultaneously.
Finally bear in mind that Cgs is fairly constant, while Cgd can change by a very large amount as Vds gets small. If you want to run the output stage to within, say less than 5V of the rails, and you want to maintain a high slew rate capability under those conditions, you really need to look out for large Cgd.
Your amplifier stability evaluation, both for global and local stability, must also take account of large values of Cgd that come into play as you approach the rails.
Cheers,
Bob
MOSFET Ft
I have had some recent experience with the BUZ901/906 and 901D/906D LDMOSFETs in regards to Ft. The latest audio amp I designed and debugged uses these devices in a source follower configuration. During debug I had some problems with oscillation and observed rail-rail (150 VPP) excursions at a frequency of approx 20 MHz, which equates to a pretty healthy slew rate. Fortunately, I was able to fix the oscillation problem, but one thing is certain: the slew rate of the output stage is far in excess of the 100 V/uS of the VAS stage, which uses bipolar devices.
Another data point comes from a 200 KHz - 5.0 MHz 200 VPP RF amplifier I have designed. The output stage again uses 901/906 devices, this time in a bridged topology to yield up to 200 VPP into a 5000 pf load. (Try getting that to be stable with feedback!).
I avoid the stability issue by using no feedback and regulating gain over many thousands of cycles with an AGC circuit. A breadboarded version of the amp works fine and meets the voltage and frequency requirements. As you probably guessed, this amp is not for audio purposes.
I have had some recent experience with the BUZ901/906 and 901D/906D LDMOSFETs in regards to Ft. The latest audio amp I designed and debugged uses these devices in a source follower configuration. During debug I had some problems with oscillation and observed rail-rail (150 VPP) excursions at a frequency of approx 20 MHz, which equates to a pretty healthy slew rate. Fortunately, I was able to fix the oscillation problem, but one thing is certain: the slew rate of the output stage is far in excess of the 100 V/uS of the VAS stage, which uses bipolar devices.
Another data point comes from a 200 KHz - 5.0 MHz 200 VPP RF amplifier I have designed. The output stage again uses 901/906 devices, this time in a bridged topology to yield up to 200 VPP into a 5000 pf load. (Try getting that to be stable with feedback!).
I avoid the stability issue by using no feedback and regulating gain over many thousands of cycles with an AGC circuit. A breadboarded version of the amp works fine and meets the voltage and frequency requirements. As you probably guessed, this amp is not for audio purposes.
When we built an amp using those devices in the same configuration, we also had a 20 MHz oscillation. It was easily corrected by adding 1 nF bypass caps from the drains (PS rails) to the heatsink (which was grounded). The important point was that the caps were close to the FETs, which kept the inductance down.
It was simple to fix, because the original Hitachi app notes warned that these would likely be required.
It was simple to fix, because the original Hitachi app notes warned that these would likely be required.
Re: MOSFET Ft
Yes, MOSFETs can oscillate at quite high frequencies! The fact that these devices have a high effective ft in combination with inter-electrode capacitances and bondwire inductances can make for local parasitic oscillations. Bear in mind that often these local oscillations have little or nothing to do with global feedback oscillations.
One thing that can blow out otherwise very robust MOSFETs is a gate-source breakdown. This is usually rated for only about 20V. Even if your drive cicuit is prevented by some means from applying more than 20V, one can get gate oxide breakdown as a result of HF oscillations in which the voltage on the gate internal to the device can well exceed that at the device terminal due to LC resonances.
Sometimes preventing oscillation in MOSFETs can be done to advantage by using close-in R-C snubbers rather than just brute force bypass capacitance or large value gate stoppers. The series RC snubber helps kill the Q of the oscillator topology. Drain to gate is a good location for such a snubber. Often, something like 100 pF and 47 ohms will do a great job. For more on these kinds of issues, see my MOSFET power amplifier paper under the publications tab on my website at www.cordellaudio.com
Cheers,
Bob
analog_guy said:
Yes, MOSFETs can oscillate at quite high frequencies! The fact that these devices have a high effective ft in combination with inter-electrode capacitances and bondwire inductances can make for local parasitic oscillations. Bear in mind that often these local oscillations have little or nothing to do with global feedback oscillations.
One thing that can blow out otherwise very robust MOSFETs is a gate-source breakdown. This is usually rated for only about 20V. Even if your drive cicuit is prevented by some means from applying more than 20V, one can get gate oxide breakdown as a result of HF oscillations in which the voltage on the gate internal to the device can well exceed that at the device terminal due to LC resonances.
Sometimes preventing oscillation in MOSFETs can be done to advantage by using close-in R-C snubbers rather than just brute force bypass capacitance or large value gate stoppers. The series RC snubber helps kill the Q of the oscillator topology. Drain to gate is a good location for such a snubber. Often, something like 100 pF and 47 ohms will do a great job. For more on these kinds of issues, see my MOSFET power amplifier paper under the publications tab on my website at www.cordellaudio.com
Cheers,
Bob
CMCL
Hi abzug,
Look here:
http://www.diyaudio.com/forums/attachment.php?s=&postid=1367089&stamp=1196786670
at Q7/Q10/Q11/Q12 and the collectors of Q13 and Q14,
or for another example our website ->schematics->front end->Q19...Q26.
Please, don't get intimidated by the complexity.
Cheers, Edmond
abzug said:
Hi abzug,
Look here:
http://www.diyaudio.com/forums/attachment.php?s=&postid=1367089&stamp=1196786670
at Q7/Q10/Q11/Q12 and the collectors of Q13 and Q14,
or for another example our website ->schematics->front end->Q19...Q26.
Please, don't get intimidated by the complexity.
Cheers, Edmond
CMCL
Hi abzug (what's your real name btw?)
I've moved the explanation to the PGP thread, which is a more appropriate place. Look here:
http://www.diyaudio.com/forums/showthread.php?postid=1408551#post1408551
Cheers, Edmond.
abzug said:Hard not to... I'm having trouble following itCan you give a quick explanation or a reference?
Hi abzug (what's your real name btw?)
I've moved the explanation to the PGP thread, which is a more appropriate place. Look here:
http://www.diyaudio.com/forums/showthread.php?postid=1408551#post1408551
Cheers, Edmond.
MOSFET ft at higher currents
In regard to vertical MOSFETs and oscillations, I should also mention that the ft of a vertical MOSFET tends to increase in proportion to its drain current in the current range usually of interest.
While the ft of an IRFP 240 may be on the order of 100 MHz at an idle bias of 150 mA, at a few amps the transconductance may get up to, say 4 S, while the input capacitances have not changed a lot. They may still be on the order of 1200 pf or so. In this case, the ft of the device calculates out to be on the order of 530 MHz.
This means that, just because there is no local parasitic oscillation under idle conditions, that does not mean that there may not be osillatory bursts as the signal swing causes higher currents to flow, increasing the effective ft of the output devices. In some cases, such oscillations may be of such a high frequency that they may not be seen on some oscilloscopes. However, often the presence of oscillatory bursts will cause THD to go up.
Finally, one effect that must also be considered is the transconductance bandwidth of the device. This is limited by the effective series resistance of the gate structure of the MOSFET, which may be distributed. This gate resistance forms a pole with the input capacitance of the device. So the 530 Mhz value calculated above, ignoring gate resistance, may be a bit optimistic in terms of describing the overall speed of the device.
Cheers,
Bob
In regard to vertical MOSFETs and oscillations, I should also mention that the ft of a vertical MOSFET tends to increase in proportion to its drain current in the current range usually of interest.
While the ft of an IRFP 240 may be on the order of 100 MHz at an idle bias of 150 mA, at a few amps the transconductance may get up to, say 4 S, while the input capacitances have not changed a lot. They may still be on the order of 1200 pf or so. In this case, the ft of the device calculates out to be on the order of 530 MHz.
This means that, just because there is no local parasitic oscillation under idle conditions, that does not mean that there may not be osillatory bursts as the signal swing causes higher currents to flow, increasing the effective ft of the output devices. In some cases, such oscillations may be of such a high frequency that they may not be seen on some oscilloscopes. However, often the presence of oscillatory bursts will cause THD to go up.
Finally, one effect that must also be considered is the transconductance bandwidth of the device. This is limited by the effective series resistance of the gate structure of the MOSFET, which may be distributed. This gate resistance forms a pole with the input capacitance of the device. So the 530 Mhz value calculated above, ignoring gate resistance, may be a bit optimistic in terms of describing the overall speed of the device.
Cheers,
Bob
MOSFET pole
Hi Bob,
I'm really concerned about that evil pole. The problem is that we need a series gate resistor, but at the same time, the Cgd of vertical MOSFETs varies enormously. From say 50pF at Vds=100V to a few nF at Vds=1V. If one tries to squeeze the last volts from an output stage and also applies a lot of NFB, this swinging pole really jeopardizes the stability. Up to now, I wasn't able to correct this nasty behavior. Any idea how to tackle this problem?
Cheers, Edmond.
Bob Cordell said:
Hi Bob,
I'm really concerned about that evil pole. The problem is that we need a series gate resistor, but at the same time, the Cgd of vertical MOSFETs varies enormously. From say 50pF at Vds=100V to a few nF at Vds=1V. If one tries to squeeze the last volts from an output stage and also applies a lot of NFB, this swinging pole really jeopardizes the stability. Up to now, I wasn't able to correct this nasty behavior. Any idea how to tackle this problem?
Cheers, Edmond.
I've simmed a "gain scheduled" feedback adjuster that uses diode-R networks to change gain as the output mosfet saturates - not likely to reduce distortion very effectively for that last dB of output but stability can be improved - BJ Lurie describes some "dynamic compensation" schemes - though mostly for saturation related applications
some metal gate mosfets are available - at least you are then in principle able to control up to package inductive parasitics - standard power mosfets use polysilicon gates that may have 10s of Ohms of resistance to the far edges of the die as Bob mentions
some metal gate mosfets are available - at least you are then in principle able to control up to package inductive parasitics - standard power mosfets use polysilicon gates that may have 10s of Ohms of resistance to the far edges of the die as Bob mentions
Re: MOSFET pole
I agree, this is a real concern, especially if one is to get the greatest potential performance out of the device. I've found that the best way to minimize the gate stopper resistor is to include a series R-C Zobel between the gate and the drain in a source follower. The key here is to avoid the local parasitic oscillations by damping out the resonances at high frequencies. I touch on this technique in my MOSFET amplifier paper. I've been able to use gate stoppers as small as 47 ohms with this technique.
I also mention in that paper that the internal gate series resistance tends to be quite a bit higher with laterals as compared to verticals.
As you point out, the Cgd begins to get really bad as Vds goes below about 10V. It is actually quite small at higher Vds. There are two keys here. First, one must avoid local parasitic oscillations from coming into play when the output gets near the rails and Cgd gets high. That gate-drain Zobel helps here. Secondly, the MOSFET wants to be driven by a low enough source impedance (including the gate stopper) that the inward movement of the pole with Cgd does not cause too much excess phase near the global NFB gain crossover frequency.
Cheers,
Bob
Edmond Stuart said:
I agree, this is a real concern, especially if one is to get the greatest potential performance out of the device. I've found that the best way to minimize the gate stopper resistor is to include a series R-C Zobel between the gate and the drain in a source follower. The key here is to avoid the local parasitic oscillations by damping out the resonances at high frequencies. I touch on this technique in my MOSFET amplifier paper. I've been able to use gate stoppers as small as 47 ohms with this technique.
I also mention in that paper that the internal gate series resistance tends to be quite a bit higher with laterals as compared to verticals.
As you point out, the Cgd begins to get really bad as Vds goes below about 10V. It is actually quite small at higher Vds. There are two keys here. First, one must avoid local parasitic oscillations from coming into play when the output gets near the rails and Cgd gets high. That gate-drain Zobel helps here. Secondly, the MOSFET wants to be driven by a low enough source impedance (including the gate stopper) that the inward movement of the pole with Cgd does not cause too much excess phase near the global NFB gain crossover frequency.
Cheers,
Bob