Hello all,
I'm designing a new board with 2x TDA1541A where user can switch between 3 modes. Regular simultaneous where both are in parallel, or balanced ("dual mono"), or signed magnitude.
Trivial question but just to confirm, if we already have simultaneous signal (LE, BCK, DL, DR), then all we need to go balanced is a simple inverter like maybe SN74LVC2GU04, just invert the DL and DR to get - versions, and then feed the DL+ DL- to one chip and sum the outputs together (for 8mA current) then current injection & resistor to ground (or do i need separate I/V resistors for each output and a 1k summing node?), same with other chip and DR+ DR-. Simple as can be right? That solves first two modes (hopefully)
But then it is still not signed magnitude. For that we need to start from scratch from I2S (if using schematic from post 7092 with * outputs if only 2 DAC's). I dont know of a schematic to go from simultaneous to signed magnitude directly...that would be nice actually.
Since one of my hobbies is looking for listings for old Philips players, managed to score another (also non A as it happens).
I never got the single to work properly as there is always severe distortion on low level sounds (say -50db). The louder sounds play fine, but anything quiet is distorted. Most i've seen point this to a DEM problem, but after experimenting with various arrangements all had the same issue, and even with nothing connected to pin 16 and 17 (as is recommended in non-A sheet). So maybe i damaged my dac trying the 50HZ DEM on a non-A, who knows. I wanted to post that board for the community, but since i cant verify it works correctly as-is and wanted to avoid giving headaches (other than through my silly questions but i appreciate your patience) i decided to move on and will post this new one to hopefully redeem myself. Although another member has asked me for the files and apparently made a beaglebone version from it that works just fine, so maybe i just messed up soldering some SMD...
OFC goes without saying none of this would be possible without John and others sharing of knowledge, thanks once again. Sorry for longish post, i hope i didnt mess anything up too bad.
I'm designing a new board with 2x TDA1541A where user can switch between 3 modes. Regular simultaneous where both are in parallel, or balanced ("dual mono"), or signed magnitude.
Trivial question but just to confirm, if we already have simultaneous signal (LE, BCK, DL, DR), then all we need to go balanced is a simple inverter like maybe SN74LVC2GU04, just invert the DL and DR to get - versions, and then feed the DL+ DL- to one chip and sum the outputs together (for 8mA current) then current injection & resistor to ground (or do i need separate I/V resistors for each output and a 1k summing node?), same with other chip and DR+ DR-. Simple as can be right? That solves first two modes (hopefully)
But then it is still not signed magnitude. For that we need to start from scratch from I2S (if using schematic from post 7092 with * outputs if only 2 DAC's). I dont know of a schematic to go from simultaneous to signed magnitude directly...that would be nice actually.
Since one of my hobbies is looking for listings for old Philips players, managed to score another (also non A as it happens).
I never got the single to work properly as there is always severe distortion on low level sounds (say -50db). The louder sounds play fine, but anything quiet is distorted. Most i've seen point this to a DEM problem, but after experimenting with various arrangements all had the same issue, and even with nothing connected to pin 16 and 17 (as is recommended in non-A sheet). So maybe i damaged my dac trying the 50HZ DEM on a non-A, who knows. I wanted to post that board for the community, but since i cant verify it works correctly as-is and wanted to avoid giving headaches (other than through my silly questions but i appreciate your patience) i decided to move on and will post this new one to hopefully redeem myself. Although another member has asked me for the files and apparently made a beaglebone version from it that works just fine, so maybe i just messed up soldering some SMD...
OFC goes without saying none of this would be possible without John and others sharing of knowledge, thanks once again. Sorry for longish post, i hope i didnt mess anything up too bad.
Hi Zbunjen,
If you already have LE, BCK, DL and DR,
(1) SE mode: feed these 4 signals to one chip.
(2) Parallel mode: feed LE, BCK, DL, DL to left channel chip, feed LE, BCK, DR, DR to right channel chip.
(3) Balanced mode (simplified, not fully correct): feed LE, BCK, DL, -DL (inverted DL) to left channel chip, feed LE, BCK, DR, -DR (inverted DR) to right channel chip.
For SE mode use one I/V resistor and +2mA bias source or active I/V converter circuit on each output.
For parallel mode you can parallel the outputs on each chip and use an I/V resistor with half the usual value and +4mA bias or active I/V converter circuit. Full scale current doubles to -8mA!
For balanced mode you can use a separate I/V resistor on each output and +2mA bias source for each of the 4 resistors. You can also use 4 separate active I/V converter circuits.
The balanced outputs can be fed directly into the balanced inputs of a (pre) amp, suitable step-up transformer with twin primary windings providing SE output & balanced output, or summing stage.
Low level distortion with the TDA1541A is usually caused by a non functioning DEM circuit, but can also be caused by a defective chip.
When pin 16 and 17 are not connected (TDA1541A), the DEM clock attempts to oscillate on parasitics. Related frequencies will be too high for reliable operation (intermittent oscillation). TDA1541A logic limiting frequency is around 6.5 MHz.
Incorrect DEM clock leads to incorrect bit currents (6 highest bits) and related low level distortion.
With the A version you always need a capacitor between pin 16 and 17 unless external clock injection is used. The non-A version (TDA1541) has the DEM timing capacitor integrated and pins 16 & 17 are not connected (NC).
DEM clock frequency is typically set to approx. 200 KHz and for this frequency we typically use 100nF decoupling caps. The ripple current caused by DEM operating @ 200 KHz is sufficiently reduced by these 100nF decoupling caps.
For 50 ... 100Hz DEM frequency we have to significantly lower the timing cap to approx. 1uF ... 2u2. The ripple current frequency will be much lower now, so 100nF won't be sufficient to reduce it. This is why we need to increase decoupling cap value to 220 ... 470uF.
The DC voltage on the decoupling pins equals approx. -8 ... -13V, so the plus of the decoupling caps now has to be connected to GND and the minus of the decoupling caps connects to the decoupling pins.
The low bit currents: -2mA, -1mA, 500uA, 250uA, 125uA and 62.5uA now have to charge the decoupling caps (-8 ... -13V). This takes time (minutes) and during this time there will be (low level) distortion.
Use decoupling caps with specified low DC leakage current and use -at least- 25 or 35V rating. Higher voltage rating with given -8 ... -13V DC on the decoupling pins results in lowest DC leakage current.
If you already have LE, BCK, DL and DR,
(1) SE mode: feed these 4 signals to one chip.
(2) Parallel mode: feed LE, BCK, DL, DL to left channel chip, feed LE, BCK, DR, DR to right channel chip.
(3) Balanced mode (simplified, not fully correct): feed LE, BCK, DL, -DL (inverted DL) to left channel chip, feed LE, BCK, DR, -DR (inverted DR) to right channel chip.
For SE mode use one I/V resistor and +2mA bias source or active I/V converter circuit on each output.
For parallel mode you can parallel the outputs on each chip and use an I/V resistor with half the usual value and +4mA bias or active I/V converter circuit. Full scale current doubles to -8mA!
For balanced mode you can use a separate I/V resistor on each output and +2mA bias source for each of the 4 resistors. You can also use 4 separate active I/V converter circuits.
The balanced outputs can be fed directly into the balanced inputs of a (pre) amp, suitable step-up transformer with twin primary windings providing SE output & balanced output, or summing stage.
Low level distortion with the TDA1541A is usually caused by a non functioning DEM circuit, but can also be caused by a defective chip.
When pin 16 and 17 are not connected (TDA1541A), the DEM clock attempts to oscillate on parasitics. Related frequencies will be too high for reliable operation (intermittent oscillation). TDA1541A logic limiting frequency is around 6.5 MHz.
Incorrect DEM clock leads to incorrect bit currents (6 highest bits) and related low level distortion.
With the A version you always need a capacitor between pin 16 and 17 unless external clock injection is used. The non-A version (TDA1541) has the DEM timing capacitor integrated and pins 16 & 17 are not connected (NC).
DEM clock frequency is typically set to approx. 200 KHz and for this frequency we typically use 100nF decoupling caps. The ripple current caused by DEM operating @ 200 KHz is sufficiently reduced by these 100nF decoupling caps.
For 50 ... 100Hz DEM frequency we have to significantly lower the timing cap to approx. 1uF ... 2u2. The ripple current frequency will be much lower now, so 100nF won't be sufficient to reduce it. This is why we need to increase decoupling cap value to 220 ... 470uF.
The DC voltage on the decoupling pins equals approx. -8 ... -13V, so the plus of the decoupling caps now has to be connected to GND and the minus of the decoupling caps connects to the decoupling pins.
The low bit currents: -2mA, -1mA, 500uA, 250uA, 125uA and 62.5uA now have to charge the decoupling caps (-8 ... -13V). This takes time (minutes) and during this time there will be (low level) distortion.
Use decoupling caps with specified low DC leakage current and use -at least- 25 or 35V rating. Higher voltage rating with given -8 ... -13V DC on the decoupling pins results in lowest DC leakage current.
Hi all,
I currently own 4 tda1541a and i2soverusb viii from jlsound
After some probing through discussions, it seems that utilizing tda1541 in simultaneous mode would benefit a lot including lower jitter so I try using tda1541 in simultaneous mode with CCDA iv stage from radioman62 and it sounds nice
I also want to try Pedja rogic diamond iv stage and paralleling tda's in unbalanced configuration,
so bunch of simple questions arise for me (I’m not EE L ) and I appreciate if anyone could clarify these for me
I currently own 4 tda1541a and i2soverusb viii from jlsound
After some probing through discussions, it seems that utilizing tda1541 in simultaneous mode would benefit a lot including lower jitter so I try using tda1541 in simultaneous mode with CCDA iv stage from radioman62 and it sounds nice
I also want to try Pedja rogic diamond iv stage and paralleling tda's in unbalanced configuration,
so bunch of simple questions arise for me (I’m not EE L ) and I appreciate if anyone could clarify these for me
- Could I use a chip for each channel just by paralleling DR, DL inputs and AOL, AOR outputs in simultaneous mode? That doesn’t lead to zero crossing problem as mentioned before or not?
- In dual mono approach (every channel benefits from separate 1541 with DR, DL paralleled) Is it necessary to link pin 16 with 100pf cap of left and right chips for clock sync?
Hello ecdesigns, thank you for your help and the details.
For parallel and balanced im a bit worried about if the 2 dac outputs (in a single chip) aren't perfectly amplitude or phase matched, then after paralleling it would result in harmonics.
To help solve these i plan to use the circuit in the first image. R5 and R6 for current injection (offset) and optionally R8 and R10 to trim the I/V resistors if there is some amplitude mismatch. C1 is just a simply LP filter cap. (image 1) I understand simple parallel does not need summing node, but segmented needs, so 2x 1k resistors (R3 and R4)? If i remove them in the sim, everything is the same so im not sure what their role is. I ask because it would be convenient if i can use same I/V for both parallel and segmented (signed magnitude) mode, either both having the 1k nodes, or both not having. Since having one resistor half in value, or two that are double is the same situation, i thought i might use the same I/V. (image 2) @koldby @Hans Polak I read a lot of your posts 1000 posts ago as well that dealt with these topics of the I/V, what do you think?
Also just to confirm, post 7092 is the latest schematic for generating signed magnitude output?
Also thank you for the additional details, I have spent many hours in this thread but still discover new tidbits from you and the others. So many posts here, its easy to miss things. Im reading Rudy van de Plaasche's thesis now, to gain more insight. Again thanks for being patient with me, im trying to do this right..
For the first question, John (ecdesigns) just gave an answer two posts right above. Feed one chip DL DL, the other DR DR, then you can parallel the outputs of each chip. Also, it does lead to zero crossing problem because the output glitch it is inherent with the MSB crossing switching all bits at the same time, leading to a larger current change that has to settle. Signed magnitude attempts to solve this by using each DAC dedicated for each half of the signal. Try reading the posts from, for example 7000 onwards, and search for key words.
Second if i understood correctly you're talking about the Grundig (or however it was called) DEM reclock? In this thread the consensus seems to be 50Hz DEM is better because of lower on chip jitter. Look in the search bar "50hz DEM schematic".
If you want i can send you a PCB i make so you can try playing with it, but no ETA on that for the moment, but im actively working on it.
First mode, completely understood
For parallel and balanced im a bit worried about if the 2 dac outputs (in a single chip) aren't perfectly amplitude or phase matched, then after paralleling it would result in harmonics.
To help solve these i plan to use the circuit in the first image. R5 and R6 for current injection (offset) and optionally R8 and R10 to trim the I/V resistors if there is some amplitude mismatch. C1 is just a simply LP filter cap. (image 1) I understand simple parallel does not need summing node, but segmented needs, so 2x 1k resistors (R3 and R4)? If i remove them in the sim, everything is the same so im not sure what their role is. I ask because it would be convenient if i can use same I/V for both parallel and segmented (signed magnitude) mode, either both having the 1k nodes, or both not having. Since having one resistor half in value, or two that are double is the same situation, i thought i might use the same I/V. (image 2) @koldby @Hans Polak I read a lot of your posts 1000 posts ago as well that dealt with these topics of the I/V, what do you think?
Also just to confirm, post 7092 is the latest schematic for generating signed magnitude output?
Also thank you for the additional details, I have spent many hours in this thread but still discover new tidbits from you and the others. So many posts here, its easy to miss things. Im reading Rudy van de Plaasche's thesis now, to gain more insight. Again thanks for being patient with me, im trying to do this right..
I ordered some Rubycon TWL for the same reason....i'll test leakage and see.
Hello, i have the same jlsounds board.
For the first question, John (ecdesigns) just gave an answer two posts right above. Feed one chip DL DL, the other DR DR, then you can parallel the outputs of each chip. Also, it does lead to zero crossing problem because the output glitch it is inherent with the MSB crossing switching all bits at the same time, leading to a larger current change that has to settle. Signed magnitude attempts to solve this by using each DAC dedicated for each half of the signal. Try reading the posts from, for example 7000 onwards, and search for key words.
Second if i understood correctly you're talking about the Grundig (or however it was called) DEM reclock? In this thread the consensus seems to be 50Hz DEM is better because of lower on chip jitter. Look in the search bar "50hz DEM schematic".
If you want i can send you a PCB i make so you can try playing with it, but no ETA on that for the moment, but im actively working on it.
Attachments
Hello,
Development continues on the "all in one" evaluation board. I might not be most talented in this thread but i will not give up.
This post is basically just an update and might be hard to read (i tried to make it as clear), but the last post with some questions was more important for finishing the board, particularly the part about needing a summing node for balanced/segmented (or not needing?) i still cannot find it out despite hours of search and spice simulation.
Here is the system i thought of that should satisfy a lot of features...possibly.
Ignore the capacitors, they are just for different footprints.
mode 1. In schematic from #7092, DOR+- are the outputs of the balanced segmented module, and with * is SE mode. These are brought to headers J7 and J9, kind of like in a DPDT switch configuration, where you use jumpers to jump the middle two pins with one set of the outer ones. The middle ones always go to the DAC (arbitrarily names R+-, L+-). We can bridge 1-3 and 2-4 on both headers and now we have balanced segmented, for example.
mode 2. If we deactivate that logic segmented module section (there is a jumper to just disconnect the LP5907-3.3 off screen), and directly plug in LEO, BCKO into header J10 and DOR into R+ and DOL into L- , each chip will only play one channel, on one dac. It is not most efficient as we are wasting 2 dacs doing nothing, and current is lower, But maybe ground bounce and crosstalk is lower since the whole dac only does one single channel.
mode 3. we now bridge 1-3 and 2-4 on J11 "patch board". Now basically the channel that we patched on J7 and J9 is copied over onto the other dac of the same chip, now we have 2x parallel, current is increased.
Mode 4. Same as above, except we bridge R+ and L+. This is a different kind of parallel but with each chip doing both channels in single ended, like you'd normally imagine.
mode 5. i thought about regular balanced mode with no signed magnitude. We invert DOR into DOR- and DOL into DOL- with a 74 series 1G04 (U17-18). This is only pseudo balanced i think, but lets see. This part of the circuit is always inert, until JP10 is bridged, giving power to the two inverters. I can always remove whatever turns out to suck in v1.1.
Onto an even bigger cognitohazard, the "all in one" passive I/V
First we have a 3 way jumper for selecting the configuration that is happening at the dac, for example when we feed normally the DAC with R+ and R- being the same signal (via bridging 1-3 and 2-4 on J11 i.e mode 3), then we would select bridging 2-3 on both of these will combine AORs and AOLs. If we selected 1-2 and 3-4 on J11 (mode 4), then we'd use 1-2 here.
We have JP3 in case we dont even want to use the onboard passive I/V and just present current to the headers, for use with external transimpedance devices. If we bridge it then we get the 61R for I/V and a 100k for trimming it, in case of amplitude mismatch due to slight resistor mismatch.
Below that we have current injection with a trimmer that ecdesigns explained in previous posts.
That was quite a post an im not sure anyone read it, honestly i dont know, usually when you tread waters where you're doing design practices other don't (like the patchboard galore stuff), then its probably not a good idea. But still, what do you think? I think this I/V might not work at all for segmented mode, or balanced, because of lack of 2x 1k summing node, but will work with parallel. That is my biggest hmm right now.
Development continues on the "all in one" evaluation board. I might not be most talented in this thread but i will not give up.
This post is basically just an update and might be hard to read (i tried to make it as clear), but the last post with some questions was more important for finishing the board, particularly the part about needing a summing node for balanced/segmented (or not needing?) i still cannot find it out despite hours of search and spice simulation.
Here is the system i thought of that should satisfy a lot of features...possibly.
Ignore the capacitors, they are just for different footprints.
mode 1. In schematic from #7092, DOR+- are the outputs of the balanced segmented module, and with * is SE mode. These are brought to headers J7 and J9, kind of like in a DPDT switch configuration, where you use jumpers to jump the middle two pins with one set of the outer ones. The middle ones always go to the DAC (arbitrarily names R+-, L+-). We can bridge 1-3 and 2-4 on both headers and now we have balanced segmented, for example.
mode 2. If we deactivate that logic segmented module section (there is a jumper to just disconnect the LP5907-3.3 off screen), and directly plug in LEO, BCKO into header J10 and DOR into R+ and DOL into L- , each chip will only play one channel, on one dac. It is not most efficient as we are wasting 2 dacs doing nothing, and current is lower, But maybe ground bounce and crosstalk is lower since the whole dac only does one single channel.
mode 3. we now bridge 1-3 and 2-4 on J11 "patch board". Now basically the channel that we patched on J7 and J9 is copied over onto the other dac of the same chip, now we have 2x parallel, current is increased.
Mode 4. Same as above, except we bridge R+ and L+. This is a different kind of parallel but with each chip doing both channels in single ended, like you'd normally imagine.
mode 5. i thought about regular balanced mode with no signed magnitude. We invert DOR into DOR- and DOL into DOL- with a 74 series 1G04 (U17-18). This is only pseudo balanced i think, but lets see. This part of the circuit is always inert, until JP10 is bridged, giving power to the two inverters. I can always remove whatever turns out to suck in v1.1.
Onto an even bigger cognitohazard, the "all in one" passive I/V
First we have a 3 way jumper for selecting the configuration that is happening at the dac, for example when we feed normally the DAC with R+ and R- being the same signal (via bridging 1-3 and 2-4 on J11 i.e mode 3), then we would select bridging 2-3 on both of these will combine AORs and AOLs. If we selected 1-2 and 3-4 on J11 (mode 4), then we'd use 1-2 here.
We have JP3 in case we dont even want to use the onboard passive I/V and just present current to the headers, for use with external transimpedance devices. If we bridge it then we get the 61R for I/V and a 100k for trimming it, in case of amplitude mismatch due to slight resistor mismatch.
Below that we have current injection with a trimmer that ecdesigns explained in previous posts.
That was quite a post an im not sure anyone read it, honestly i dont know, usually when you tread waters where you're doing design practices other don't (like the patchboard galore stuff), then its probably not a good idea. But still, what do you think? I think this I/V might not work at all for segmented mode, or balanced, because of lack of 2x 1k summing node, but will work with parallel. That is my biggest hmm right now.
After reading and double reading i realised something silly. For trimming outputs due to mismatch, we have these 100K pots in parallel with the I/V, (in my case, RV3 and RV3) however in my implementation currents are already summed before that, so there's basically no point, its just trimming both combined already. I will keep them in the schematic but probably not install them on the board.
Summing nodes are only if trimming procedure is desired, it has nothing to do with SE vs balanced as i was mixing up in my head leading me to confusion.
So i suppose then the answer to the post 2 posts ago is yes, you can just combine outputs in signed magnitude mode, then have 1 I/V resistor, some current injection (or in our case ground lift), and that's that?
Btw, here's a little board teaser. I spent quite a lot of time thinking about current return paths for everything, it is 4 layer (mandatorily), and i managed to not only have every trace on the board have a clean uninterupted ground underneath, but also manage how those grounds are even coupled between themselves, and so on.
Digital and analog sections are connected just above pin 4 and pin 14 and even here i made sure they cant disturb the DEM decoupling cap currents. There is a lot more here but that is to come, if anyone even reads these posts
Summing nodes are only if trimming procedure is desired, it has nothing to do with SE vs balanced as i was mixing up in my head leading me to confusion.
So i suppose then the answer to the post 2 posts ago is yes, you can just combine outputs in signed magnitude mode, then have 1 I/V resistor, some current injection (or in our case ground lift), and that's that?
Btw, here's a little board teaser. I spent quite a lot of time thinking about current return paths for everything, it is 4 layer (mandatorily), and i managed to not only have every trace on the board have a clean uninterupted ground underneath, but also manage how those grounds are even coupled between themselves, and so on.
Digital and analog sections are connected just above pin 4 and pin 14 and even here i made sure they cant disturb the DEM decoupling cap currents. There is a lot more here but that is to come, if anyone even reads these posts
No replies, so nobody is interested? One of the largest threads on the entire forum drops off a cliff as soon as i show up
Anyway, I have 47uf 25V Rubycon TWL low leakage caps, i was thinking parallel x2 to get 100uF but half the ESR.
But also then, use only one on LSB (pin 24 & 7), because smaller current doesnt need 100uF, but at the same time have lower leakage current.
And also use 3x parallel for MSB (pin 13&18), because it provides the biggest output change and more decoupling might help? (and also even lower ESR)
Does that stand to reason or am i mistaken?
Anyway, I have 47uf 25V Rubycon TWL low leakage caps, i was thinking parallel x2 to get 100uF but half the ESR.
But also then, use only one on LSB (pin 24 & 7), because smaller current doesnt need 100uF, but at the same time have lower leakage current.
And also use 3x parallel for MSB (pin 13&18), because it provides the biggest output change and more decoupling might help? (and also even lower ESR)
Does that stand to reason or am i mistaken?
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Hi, I have read some of your posts. I haven't built any 1541 dac yet, I just thought about it (a few times) and worked out how I will do it. I'll eventually get to it.
Your idea on the post above (parallel electrolytics of same size) looks good to me. Probably a good idea to use three on the MSB and one on the LSB, but I don't have the experience so I can't confirm. Maybe somebody will give an answer to that.
What I would point out is that small smd bypass caps can be a problem. This usually creates a resonance with the big cap and the impedance at the resonant frequency can be quite high causing a "noise peak".
Your idea on the post above (parallel electrolytics of same size) looks good to me. Probably a good idea to use three on the MSB and one on the LSB, but I don't have the experience so I can't confirm. Maybe somebody will give an answer to that.
What I would point out is that small smd bypass caps can be a problem. This usually creates a resonance with the big cap and the impedance at the resonant frequency can be quite high causing a "noise peak".
Hello thanks for reply.
Yes you are right, resonance may occur but not because of the caps, but because if there is inductance (such as from traces or lead inductance) it forms an RC circuit. In this case traces are pretty short and thick (you can see on PCB image above) but its a valid concern. Anyway i dont think i will install them anyway, because on 50HZ dem frequency is so low, small smd will not help much. But i left it anyway because someone might wish to run circuit with other dem freq or whatever, so they have option to install this, in theory i didnt imagine both the larger lytics and small smd's being used at the same time, its just how you configure this board..
I have it in front of me, will build over next weeks still waiting for some parts to come.
Hopefully at least something on it works..
Yes you are right, resonance may occur but not because of the caps, but because if there is inductance (such as from traces or lead inductance) it forms an RC circuit. In this case traces are pretty short and thick (you can see on PCB image above) but its a valid concern. Anyway i dont think i will install them anyway, because on 50HZ dem frequency is so low, small smd will not help much. But i left it anyway because someone might wish to run circuit with other dem freq or whatever, so they have option to install this, in theory i didnt imagine both the larger lytics and small smd's being used at the same time, its just how you configure this board..
I have it in front of me, will build over next weeks still waiting for some parts to come.
Hopefully at least something on it works..
Your welcome.
OK, good idea having the option for both low freq and high freq d.e.m.
Yes, of course, the cause of the resonance is inductance/ESL of cap which forms an RLC circuit with the bypass. I really liked the link that someone posted recently: https://www.falstad.com/circuit/
If you go to AC Circuits -> Parallel Resonance it gives a nice visual representation where we can see that, at resonance, it looks like the reactive part of the circuit is disconnected, it makes no difference. This is the ideal case of course; real circuits always have resistance and the "disconnection" is not total.
Good luck with the project
OK, good idea having the option for both low freq and high freq d.e.m.
Yes, of course, the cause of the resonance is inductance/ESL of cap which forms an RLC circuit with the bypass. I really liked the link that someone posted recently: https://www.falstad.com/circuit/
If you go to AC Circuits -> Parallel Resonance it gives a nice visual representation where we can see that, at resonance, it looks like the reactive part of the circuit is disconnected, it makes no difference. This is the ideal case of course; real circuits always have resistance and the "disconnection" is not total.
Good luck with the project
I'm attaching an idea for a DC coupled I-V converter circuit.
This common base I-V converter with folded cascode ticks a number of boxes. It has very low input impedance over a wide bandwidth thanks to the discrete servo (long tailed pair with current mirror). The other servo (opamp DC servo) is not conventional either, and should be neutral in terms of sound. The current sources see very little voltage swing and work better this way. I intend to power the circuit from the same regulators that power the '1541.
I simulated it in Microcap 12 (which is now free) and it seems to be stable without compensation. I fed it a 100 KHz sine wave (4mA peak-peak, 2mA DC sink to emulate the signal amplitude of the '1541). Distortion is low and monotonic: the second harmonic is about -80dB in respect to the output of 4V peak-peak, successive harmonics fall and the fifth is well under -100dB. I used 100KHz in an attempt to be fair because the actual input will be a staircase of course. Hopefully this simulation gives an idea of the performance.
I have already experimented with a few different analog stages, but with other dacs such as 1543, 1545 and AD1865. Passive I-V with low value resistors and a low noise gain stage is also a contender. I like it, but I also had good results with current steering circuits like this one. It is one more option to try.
Thanks,
Alex
This common base I-V converter with folded cascode ticks a number of boxes. It has very low input impedance over a wide bandwidth thanks to the discrete servo (long tailed pair with current mirror). The other servo (opamp DC servo) is not conventional either, and should be neutral in terms of sound. The current sources see very little voltage swing and work better this way. I intend to power the circuit from the same regulators that power the '1541.
I simulated it in Microcap 12 (which is now free) and it seems to be stable without compensation. I fed it a 100 KHz sine wave (4mA peak-peak, 2mA DC sink to emulate the signal amplitude of the '1541). Distortion is low and monotonic: the second harmonic is about -80dB in respect to the output of 4V peak-peak, successive harmonics fall and the fifth is well under -100dB. I used 100KHz in an attempt to be fair because the actual input will be a staircase of course. Hopefully this simulation gives an idea of the performance.
I have already experimented with a few different analog stages, but with other dacs such as 1543, 1545 and AD1865. Passive I-V with low value resistors and a low noise gain stage is also a contender. I like it, but I also had good results with current steering circuits like this one. It is one more option to try.
Thanks,
Alex
That is nice Alexandre. Thanks.
Few questions please
BF245A, J112, LSK170...? Ids is critical ? As noise ?
Should the leds to be lowest noise or it doesn't care there ? HLMP6000 red led?
AD825 for the servo ?
What one should use for the transistors TO-92?
Do you prefer that tipology over a current miror with same jfet used at ccs for the TDA1541 ?
Edit: is there a way to avoid too much V offset at dc coupling output with a trimpot ? 200E trimpot in spite of R11 ? Or at R3 ? (I am a total noob with low understanding here so surely an odd question)
Few questions please
BF245A, J112, LSK170...? Ids is critical ? As noise ?
Should the leds to be lowest noise or it doesn't care there ? HLMP6000 red led?
AD825 for the servo ?
What one should use for the transistors TO-92?
Do you prefer that tipology over a current miror with same jfet used at ccs for the TDA1541 ?
Edit: is there a way to avoid too much V offset at dc coupling output with a trimpot ? 200E trimpot in spite of R11 ? Or at R3 ? (I am a total noob with low understanding here so surely an odd question)
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Your welcome. BF245A is a good choice, so is 2SK30, 2SK246 or even LM334 (read datasheet). Idss not critical, and no need for ultra low noise. You just have to adjust the current with R10. And you should choose leds that give you 1.9V to 2V around 2-3 mA. I bought a few types of leds and chose the ones with the correct voltage. I checked them for noise and didn't find any noisy outliers, I think most are OK. You can fine adjust the current (R10) to get close to 2V or a bit less such as 1.9V. This is not critical, it will not affect DC offset at the output which will be dictated by the precision of the opamp.
Normally there are no trims when a servo is used because that is its function - to trim. It will take care of drift with temperature which is nice. AD825 is almost overkill, you can certainly use it. The opamp must have JFET inputs and can be inexpensive such as OPA134, maybe TL071 / TL081 too, but these have slightly higher DC offset than an OPA627 for example. Simulation with OPA134 shows 0.004 mV, that is 4 uV, but I'm not sure what it will be in practice. BTW, I just realized that it is better to supply the opamp from -15V and +5V, this can avoid a latch-up which can occur if input voltage exceeds the supply. Important: the output can only be connected after the servo settles, about 10 seconds in simulations. Must be checked in real life. Otherwise the DC can damage pots and speakers.
Transistors should be TO-92 or the slightly taller TO-92MOD, many choices here. I hear Zetex and ROHM are very good. Check the datasheets for ft: Gain Bandwidth Product vs. Collector Current, which should be near 100MHz at low current (2mA). Common types will do the job, BC550C BC560C, 2SA970BL 2SC2240BL if they are available. I simulated with BC546B and BC556B, but it doesn't hurt to use C - higher beta, it should help the distortion (which is already low). Also, try making R6=330 ohms for even lower distortion and still monotonic at 100KHz full scale input (fifth harmonic is under -120dB with R6=330 ohms).
This type of circuit when done with jfets will be a different animal. Distortion will be higher for sure but that doesn't tell all about the sound. I will build with jfets but it will be very different from this, it will be a low noise gain stage after passive I-V. About current mirrors, I only remember two such schematics: Koldby posted one for the 1543, IIRC, and the other is this: http://tech.juaneda.com/en/projects/jundacfive.html. If you know of any others I'd take a look. Current mirrors do not simulate well in my experience so far, this is all I can say.
Thanks,
Alex
Normally there are no trims when a servo is used because that is its function - to trim. It will take care of drift with temperature which is nice. AD825 is almost overkill, you can certainly use it. The opamp must have JFET inputs and can be inexpensive such as OPA134, maybe TL071 / TL081 too, but these have slightly higher DC offset than an OPA627 for example. Simulation with OPA134 shows 0.004 mV, that is 4 uV, but I'm not sure what it will be in practice. BTW, I just realized that it is better to supply the opamp from -15V and +5V, this can avoid a latch-up which can occur if input voltage exceeds the supply. Important: the output can only be connected after the servo settles, about 10 seconds in simulations. Must be checked in real life. Otherwise the DC can damage pots and speakers.
Transistors should be TO-92 or the slightly taller TO-92MOD, many choices here. I hear Zetex and ROHM are very good. Check the datasheets for ft: Gain Bandwidth Product vs. Collector Current, which should be near 100MHz at low current (2mA). Common types will do the job, BC550C BC560C, 2SA970BL 2SC2240BL if they are available. I simulated with BC546B and BC556B, but it doesn't hurt to use C - higher beta, it should help the distortion (which is already low). Also, try making R6=330 ohms for even lower distortion and still monotonic at 100KHz full scale input (fifth harmonic is under -120dB with R6=330 ohms).
This type of circuit when done with jfets will be a different animal. Distortion will be higher for sure but that doesn't tell all about the sound. I will build with jfets but it will be very different from this, it will be a low noise gain stage after passive I-V. About current mirrors, I only remember two such schematics: Koldby posted one for the 1543, IIRC, and the other is this: http://tech.juaneda.com/en/projects/jundacfive.html. If you know of any others I'd take a look. Current mirrors do not simulate well in my experience so far, this is all I can say.
Thanks,
Alex
Hi Zbunjen,
Good to know somebody is following up on the sign magnitude design. Unfortunately I don't have time to finish my project however I have an assembled but not fully tested board based on the schematic in this post:
https://www.diyaudio.com/community/...ate-nos-dac-using-tda1541a.79452/post-5857535
If you are interested I can send it to you as a reference to play with. Hopefully it could be useful to get the final desing with dual TDAs done.
Reach out to me over PM.