IMHO chip is great but datasheet, App Note and even .h file generated by PPC3 are messys.
What's the problem with .h file ?
Process flows appnote (SLAA799A) on page 87 confirm the requirement of a delay between the configuration and startup of the SAI (let’s call it the input stage and clock generator of the chip) and the DSP.
The issue in the PPC3 generated .h file is that they alternate configuration intended to the SAI with configuration intended to the DSP. That was JMF11's issue using a 2.1 configuration which use the sub-channel (TAS as a left, a right and a sub channel). In the JMF ppc file the sub channel was activated just after a command targeted to the SAI, and as sub channel activation is a DSP duty, delay constraint between SAI setup and DSP setup wasn’t respected causing DSP to behave badly (I don’t remember if it was muting or not behaving as expected).
This is not easy to explain, because it is a line by line analysis of the .h file. But IMHO that’s was the issue and inserting random large number of 00,00 solved the issue and confirmed the existence of the delay constraint. Inserting 0, or using meta-command is just a way to solve the issue, what really matter is identifying the root cause. But it is true that using zero is not recommanded as delay become dependant of I2C speed, and PPC3 generated file may not work at 400kHz I2C.
To make short, current solution I use in my software and on my current NeatAMP based ongoing project is to strictly separate the configuration data (intended to the SAI and everything except the DSP) and the coefficient data only intended to the DSP. Practically speaking DSP data are in book 0x8C, other data are in others book.
At startup (cold or warm, and I’ve use cases where warm startup are mandatories) I load the config data (set SAI, clocking, wait and start DSP) then wait then load the DSP data, then un-mute. This is mainly what is described in SLAA799A P87. To do this it’s necessary to modify the PPC3 generated .h file in order to have the clear split between config /DSP data and some other thing such as swap command.
Retrospectively speaking, main issue I did encounter when debugging my NeatAMP was :
• Bad soldering of TAS
• Lack of understanding of operation and configuration of the chip, mainly due to the fact DS is 50% wrong.
• Non-functional PPC3 software until TI fixed it
• Loading sequence of the TAS : what is summarized in SLAA799A P87.
Consequences of the fourth point look like the problem kne226 has.
Chris
What's the problem with .h file ?
Process flows appnote (SLAA799A) on page 87 confirm the requirement of a delay between the configuration and startup of the SAI (let’s call it the input stage and clock generator of the chip) and the DSP.
The issue in the PPC3 generated .h file is that they alternate configuration intended to the SAI with configuration intended to the DSP. That was JMF11's issue using a 2.1 configuration which use the sub-channel (TAS as a left, a right and a sub channel). In the JMF ppc file the sub channel was activated just after a command targeted to the SAI, and as sub channel activation is a DSP duty, delay constraint between SAI setup and DSP setup wasn’t respected causing DSP to behave badly (I don’t remember if it was muting or not behaving as expected).
This is not easy to explain, because it is a line by line analysis of the .h file. But IMHO that’s was the issue and inserting random large number of 00,00 solved the issue and confirmed the existence of the delay constraint. Inserting 0, or using meta-command is just a way to solve the issue, what really matter is identifying the root cause. But it is true that using zero is not recommanded as delay become dependant of I2C speed, and PPC3 generated file may not work at 400kHz I2C.
To make short, current solution I use in my software and on my current NeatAMP based ongoing project is to strictly separate the configuration data (intended to the SAI and everything except the DSP) and the coefficient data only intended to the DSP. Practically speaking DSP data are in book 0x8C, other data are in others book.
At startup (cold or warm, and I’ve use cases where warm startup are mandatories) I load the config data (set SAI, clocking, wait and start DSP) then wait then load the DSP data, then un-mute. This is mainly what is described in SLAA799A P87. To do this it’s necessary to modify the PPC3 generated .h file in order to have the clear split between config /DSP data and some other thing such as swap command.
Retrospectively speaking, main issue I did encounter when debugging my NeatAMP was :
• Bad soldering of TAS
• Lack of understanding of operation and configuration of the chip, mainly due to the fact DS is 50% wrong.
• Non-functional PPC3 software until TI fixed it
• Loading sequence of the TAS : what is summarized in SLAA799A P87.
Consequences of the fourth point look like the problem kne226 has.
Chris
Hi knee266,
Have you tried to add zeroes’ has suggested by Jean-Marc? it’s an easy trial.
You could try to add 40 line of ‘{ 0x00, 0x00 },’ just before ‘//write co-efficients’.
Are you running I2C @100kHz or 400kHz ?
Could you describe your .h file ?
It looks like it’s a 4 wires (with MCLK and no PLL) stereo (2.0, no sub) and ‘clock auto set’ mode configuration. There’s no channel swap or mix : 100% of left go to left, same for right.
It has complex filtering scheme which use filter Biquads #4,5,6,7,9,10,12,13 and 14.
It use undocumented register (at least within SLAA799A) B0x8C, P0x1F Reg0x24 and 0x30 which seems to be related to Automatic Gain Limiter.
Could you try with a simple low pass filter using only one BQ ? to see if there’s a difference between the EVM and your board. If not, maybe you should start searching on the hardware side.
I’ll try to load your file in my board later.
Chris
Hi Chris,
I haven't had any problems with the files of ppc3, worked since day 1. Probably I was "late enough" so TI fixed the issues before I used the tas3251 for the first time.
I optimised the startup process a bit on base of the process flows datasheet.
Code:
//pull dac mute high
port_pin_set_output_level(PIN_DAC_MUTE, 1);
delay_us(100);
//switch to page 0 and book 0
tas3251m_change_book(0);
//config SAI
//Ignore MCLK error and clock halt detection (p. 78)
data[0] = 0x25;
data[1] = 0x18;
i2c_local_send(AMP175_ADR, data, 2);
//PLL reference clock is SCLK (p. 68)
data[0] = 0x0d;
data[1] = 0x10;
i2c_local_send(AMP175_ADR, data, 2);
//set DSP to normal operation
data[0] = 0x02;
data[1] = 0x00;
i2c_local_send(AMP175_ADR, data, 2);
delay_ms(5);
//pull amp reset high
port_pin_set_output_level(PIN_RESET_AMP, 1);0. DAC_MUTE and RESET_AMP are hardware pulled down. I2S clocks are already running.
1. pull DAC_MUTE high
2. Wait 100 us
3. configure SAI
(4. mute or pulling low reset_amp: reset_amp is already low)
5. put dsp to normal operation
6. wait 5 ms
7. pull RESET_AMP high.
--> Amp is ready to play.
So the amp is playing as it should. But I get a small but noticeable click/pop noise after the reset_amp pin goes high (fullrange speaker with 90 dB/W/m and passive crossover connected). I use 33 nF as the c_start. I tried 100 nF as well, but that doesn't fix the click noise.
I checked the startup sequence with the scope. I found out that I even get another spike in the moment when the pvdd is hard switched on (psu is running, connect psu and amp with a switch in the cable).
I know that problem from the tas5825m. It has also been a long procedure to get that amp click/pop free.
I think other users of the tas3251 will have that problem too. Has anyone already checked the startup sequence with the scope or has the same click/pop issue when the output stage starts switching?
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TAS startup
No problem with click/pop noise at amp startup. But I did encounter this phenomena at the very beginning of my tests. The 10uF ecap at the input of the amp where reversed, they were leaking thus producing small DC bias at the output then producing click noise when toggling Reset PIN (we always learn with errors…).
If your issue is not DC Bias related you could try to rise significantly your two delays, go 100ms for both. The DAC output stage use a symetrical supply where negative rail is supplied by a charge pump clocked by the clock system based either on MCLK or the PLL. If negative rail is not stabilized when Class D PWM start you may hear such click noise. According to your startup file your running 3 wires mode with the PLL.
While writing this message and reading your startup file I just realize that I do not understand how it currently work : the PLL is not enabled, you should write 0x01 in Reg 4 of Page 0 Book 0 to do so.
Chris
No problem with click/pop noise at amp startup. But I did encounter this phenomena at the very beginning of my tests. The 10uF ecap at the input of the amp where reversed, they were leaking thus producing small DC bias at the output then producing click noise when toggling Reset PIN (we always learn with errors…).
If your issue is not DC Bias related you could try to rise significantly your two delays, go 100ms for both. The DAC output stage use a symetrical supply where negative rail is supplied by a charge pump clocked by the clock system based either on MCLK or the PLL. If negative rail is not stabilized when Class D PWM start you may hear such click noise. According to your startup file your running 3 wires mode with the PLL.
While writing this message and reading your startup file I just realize that I do not understand how it currently work : the PLL is not enabled, you should write 0x01 in Reg 4 of Page 0 Book 0 to do so.
Chris
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I went back to the datasheet and did a quick check: PLL is by default activated upon reset, no need to write 0x01 in Reg4.
But, In order to activate the 3 wire mode, I do as you do : write 0x10 in Reg0x0D. But now, I think it has no effect as DS says that “This bit is ignored and overriden in clock auto set mode” and we’re running clock auto set mode as bit 1 of Reg0x25 is set to zero in our respective startup sequence.
That means that in “auto clock set mode” the TAS automatically detect either 4 or 3 wire mode and that it’s not required to write something in Reg0x4 and 0x0D. I’ll check this later.
Chris
Yes, I also had a closer look on the datasheet yesterday. Clock section is in auto set mode by default. So nothing to do for standard operation. I'm wondering how the switch from 48 kHz to 96 kHz sample rate is done. I mean, the amp does not know that there are any process flows. These are just combinations of functions to use the processing power of the dsp. When I look at the clock setting in the datasheet it's getting clearer to me, why there is so much config data needed to initialise a process flow without any processing e.g. filters.
I thought, that setting the 3 wire mode manually is not necessary. I did a test a few mins ago, the amp does need both additional commands (ignore mclk errors and set pll reference to sclk). That matches my initially ppc3 file. I exported a standard 48k process flow .h file and then went through it and deleted everything unnecessary until I had the config posted in #343.
You have to write in the registers 0x25 and 0x0d. Otherwise the amp wasn't working in my config. PLL will be started/used automatically, so no need to write in 0x04.
I will do some testing with larger delays to prevent from click noise.
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I spent some time today on my project and I can confirm, like you said, that writing to 0x0d id mandatory in order to select SCK as master clock for the PLL. It’s one additional error in the DS.
About you click noise have you tried to lift on leg of the 4 inputs cap at the input of the Class D amp ? Then measure differential output voltage of DAC when muted and if not zero, try to trim it with Reg 0x4E and 0x4F.
@knee266 : I did play your file without issue, it’s mainly a low pass, but sometimes it looks like there's some reverb !?. Do you have a 4 wires source with MCK ?, if so you could try to change your line 64 : { 0x0d, 0x10 }, to { 0x0d, 0x00 }, .
Rgds
About you click noise have you tried to lift on leg of the 4 inputs cap at the input of the Class D amp ? Then measure differential output voltage of DAC when muted and if not zero, try to trim it with Reg 0x4E and 0x4F.
@knee266 : I did play your file without issue, it’s mainly a low pass, but sometimes it looks like there's some reverb !?. Do you have a 4 wires source with MCK ?, if so you could try to change your line 64 : { 0x0d, 0x10 }, to { 0x0d, 0x00 }, .
Rgds
Hello AIM65,
I use I2S (4 wire) to input the DSP, and 0x0d is already 0x00, I may need to make some other adjustments.
I bought a UMIK-1 microphone. I am not familiar with ROOM EQ settings at the moment, but I found that the .h output file has some different with PPC3. I am now compare what is different.
thank you.
I use I2S (4 wire) to input the DSP, and 0x0d is already 0x00, I may need to make some other adjustments.
I bought a UMIK-1 microphone. I am not familiar with ROOM EQ settings at the moment, but I found that the .h output file has some different with PPC3. I am now compare what is different.
thank you.
Hi all,
I took the opportunity of the Christmas leaves to build 2 more boards. It worked smoothly, even if, for me, the soldering of the TAS3251 is always sort of an achievement.
I complemented my Github site with a page on my board building sequence and power-up sequence:
Board building and powering sequence * jmf13/NeatAmpTAS3251 Wiki * GitHub
Top page is:
GitHub - jmf13/NeatAmpTAS3251: Software part of the NeatAmp based on the TAS3251 chip
Time now to experiment with one board controlling the others for a Multi Channels integrated system
Happy New Year, with many audio achievements and experiments !
JMF
I took the opportunity of the Christmas leaves to build 2 more boards. It worked smoothly, even if, for me, the soldering of the TAS3251 is always sort of an achievement.
I complemented my Github site with a page on my board building sequence and power-up sequence:
Board building and powering sequence * jmf13/NeatAmpTAS3251 Wiki * GitHub
Top page is:
GitHub - jmf13/NeatAmpTAS3251: Software part of the NeatAmp based on the TAS3251 chip
Time now to experiment with one board controlling the others for a Multi Channels integrated system
Happy New Year, with many audio achievements and experiments !
JMF
Attachments
Happy new year JMF! May the NeatAmp come to live in 2021
Amp is already alive
It is just that now that they are working very well, I'm slow to finish a nice boxed design, and pulld toward different projects.I wonder if it would make sense to go to official Open Hardware for such project:
Open Source Hardware Certifications For June 2020 | Make:
Arduino programming is efficient. I now have:
- code for the slave board,
- code for the master board to configure and control both boards (and TAS3251) with I2C,
- both boards receive the same I2S.
For the moment, they play the same thing (same config file to both boards).
I have to think a bit about how to "differentiate" the two boards. My current idea is to have the same DSP config file for both, and to manually adjust the Input Mixer to:
- use only I2S Left for Master (associated to Left speaker),
- use only I2S Right for Slave (associated to Right speaker).
- code for the slave board,
- code for the master board to configure and control both boards (and TAS3251) with I2C,
- both boards receive the same I2S.
For the moment, they play the same thing (same config file to both boards).
I have to think a bit about how to "differentiate" the two boards. My current idea is to have the same DSP config file for both, and to manually adjust the Input Mixer to:
- use only I2S Left for Master (associated to Left speaker),
- use only I2S Right for Slave (associated to Right speaker).
Hi,
I uploaded on Github Arduino sketches for a 2 boards configuration for 2 ways active speakers, like LX-Mini, but applicable to any similar config):
- sketch for the slave board, where the uC only monitors power and overloads,
- sketch for the master board, where the uC configures both DSP, activates the slave board, manage volume for both boards, and manages the protection of the master board.
The use case is built with a lowpass filter and high pass filter with 2500 Hz cut-off freq. It has been generated using the PPC tool.
I have the much more complex configuration for the LX-minis working, which is working fine.
Now time to pack both boards in a nice bow, with a Meanwell LRS-350 powering both boards and an asynchronous USB to I2S board like USB digital interface AS318B PCM1536 DSD1024 compatible with Amanero Italy XMOS to I2S|Digital-to-Analog Converter| - AliExpress
JMF
I uploaded on Github Arduino sketches for a 2 boards configuration for 2 ways active speakers, like LX-Mini, but applicable to any similar config):
- sketch for the slave board, where the uC only monitors power and overloads,
- sketch for the master board, where the uC configures both DSP, activates the slave board, manage volume for both boards, and manages the protection of the master board.
The use case is built with a lowpass filter and high pass filter with 2500 Hz cut-off freq. It has been generated using the PPC tool.
I have the much more complex configuration for the LX-minis working, which is working fine.
Now time to pack both boards in a nice bow, with a Meanwell LRS-350 powering both boards and an asynchronous USB to I2S board like USB digital interface AS318B PCM1536 DSD1024 compatible with Amanero Italy XMOS to I2S|Digital-to-Analog Converter| - AliExpress
JMF
Hi,
Are you planning to make these amps with I2S input available to buy?
I noticed ChipDip.ru has similar amp, but I think it's not possible to order from them if you live outside Russian Federation.
RDC2-0050, Усилитель мощности класса D с цифровым входом I2S, 175Вт Stereo, TAS3251 | купить в розницу и оптом
It would be great to feed these amps with a DSP and use them for active speakers.
Are you planning to make these amps with I2S input available to buy?
I noticed ChipDip.ru has similar amp, but I think it's not possible to order from them if you live outside Russian Federation.
RDC2-0050, Усилитель мощности класса D с цифровым входом I2S, 175Вт Stereo, TAS3251 | купить в розницу и оптом
It would be great to feed these amps with a DSP and use them for active speakers.
Hello,
There is no foreseen Group Buy for this amplifier. It is more to be seen as an Open Hardware design on which the community can develop applications.
It is exactly designed for the use case you have in mind. The TAS3251 integrates a DSP and you can "chain" boards for active speakers. This is what I do with my LX-Mini speakers: two boards to drive the pair of speakers with the integrated DSP performing the filtering.
If interested, I still have two semi populated boards, last ones (see previous posts for more info).
Best regards,
JM
There is no foreseen Group Buy for this amplifier. It is more to be seen as an Open Hardware design on which the community can develop applications.
It is exactly designed for the use case you have in mind. The TAS3251 integrates a DSP and you can "chain" boards for active speakers. This is what I do with my LX-Mini speakers: two boards to drive the pair of speakers with the integrated DSP performing the filtering.
If interested, I still have two semi populated boards, last ones (see previous posts for more info).
Best regards,
JM
JM,
Thanks for your reply. It looks very tempting to get my hands on those last 2 boards, but it seems that the programming will be a little (too much) over my head, even thou I am planning to use the integrated DSP and use an ADAU1452 instead (finally got my head around SigmaStudio)
Anyways, the price is still the same shown before?
Also, got to ask... any impressions on how they sound?
Cheers
Thanks for your reply. It looks very tempting to get my hands on those last 2 boards, but it seems that the programming will be a little (too much) over my head, even thou I am planning to use the integrated DSP and use an ADAU1452 instead (finally got my head around SigmaStudio)
Anyways, the price is still the same shown before?
Also, got to ask... any impressions on how they sound?
Cheers
Hi,
On my Tannoy Berkeley and my LX-Mini, they have the charasteristic sound of this TPA32xx familly: dynamic, very transparent, neutral sound. The TAS3251 is the "best of TI" integration of their key components by their engineers.
It gives the sound of the source and of the speakers. Fully meets my expectations. Integration in the chip means by the way that you can't play with Opamps to alter the sound to your taste.
Small package with significant power to interface directly to a digital source.
For the price, it is Price: 30€ per partially populated board + Shipping. Soldering the TAS3251 is the main difficulty (at least for me). For the software, it needs to have a small experience with Arduino or uC programming. This is not rocket science, but not everybody had to do that before.
On my Tannoy Berkeley and my LX-Mini, they have the charasteristic sound of this TPA32xx familly: dynamic, very transparent, neutral sound. The TAS3251 is the "best of TI" integration of their key components by their engineers.
It gives the sound of the source and of the speakers. Fully meets my expectations. Integration in the chip means by the way that you can't play with Opamps to alter the sound to your taste.
Small package with significant power to interface directly to a digital source.
For the price, it is Price: 30€ per partially populated board + Shipping. Soldering the TAS3251 is the main difficulty (at least for me). For the software, it needs to have a small experience with Arduino or uC programming. This is not rocket science, but not everybody had to do that before.