Do you think 4.7 ohm is a good candidate for Q1 bias resistor in the 6-24 crossover when using a 2SK170BL with 8-9mA Idss at Q1? We will keep it original at Q2 and Q2 bias resistor with a 100 ohm resistor.
Usually I'm finding much less cumbersome just doing it, and hopping to something else, instead of too much thinking
Not saying that I'm specifically aware of all things in this thread, but sometimes I have impression that several pages are wasted on JFet biasing (resistors)
Maybe that's just me ......
Not saying that I'm specifically aware of all things in this thread, but sometimes I have impression that several pages are wasted on JFet biasing (resistors)
Maybe that's just me ......
I would have avoided that by reading every post.Yeah, I think I caused some confusion when I drew a schematics for measuring the Id of a j113 degenerated by a fixed resistor as a current source.
I was had trouble with the classic JFET testing schematic from NP, and your schematic worked, at least for the J113 and I got 7.6-8mA Idss. But I found out it did not work for 2SK170, since I knew the correct Idss from Alweit and other reputable sellers. Still not certain NPs schematic can be used for J113 for testing Idss, I will try again later tonight, in my new 2SK170 testing circuit.This very simple (in my country the proverb: simple as wood wedges) diagram always work.
In the first time try to test K170 Idss at 0V (G-S shorted).
Then select FETs which are have greater IDSS, than estimated CCS current, and measure its as CCS.
Few days ago I tested few hundred FETs (J113, J310, K117 and K170) - I found its one of my hidden boxes
- for IDSS and as CCS.Sadly all K170 in GR range (below 6.5mA).
it's easy as this:
-measure DUT full IDss
-match/group them in pairs, triplets, whatever, if needed
-if goal is specific Iq (as lower CCS in non-complementary JFet buffer), insert 200R trimpot in between DUT source and neg rail, set trimpot for desired Iq, pull DUT out, measure trimpot value, write down that value and nearest standard resistor value, for later use; for that ones (JFets) you can use leftovers, those not having matched counterpart
I mean, really - we are here for fun, to learn things, but simple things/routines are easy to find ( thus not repeat) with some ggl ingenuity, if Forum Search function isn't ( it wasn't in past, with old board) up to task
-measure DUT full IDss
-match/group them in pairs, triplets, whatever, if needed
-if goal is specific Iq (as lower CCS in non-complementary JFet buffer), insert 200R trimpot in between DUT source and neg rail, set trimpot for desired Iq, pull DUT out, measure trimpot value, write down that value and nearest standard resistor value, for later use; for that ones (JFets) you can use leftovers, those not having matched counterpart
I mean, really - we are here for fun, to learn things, but simple things/routines are easy to find ( thus not repeat) with some ggl ingenuity, if Forum Search function isn't ( it wasn't in past, with old board) up to task
OK. I really confused you guys.
Again, IDSS, by definition, means the current that flow when the gate and source pins are at the same voltage (which is the case if you short the two pins together).
The circuit Papa described measures IDSS., and you can use it for j113 as well. (You may want to adjust the resistor value for high IDSS parts). Incidentally, the range of Idss for j113 is quite large and the ones I've tested all have IDSS somewhat above 10mA.
The diagram I posted include a resistor between the gate and source. It does not measure IDSS. since having that resistor makes the voltage at the gate lower than that of the source and make the j113 conduct less current than IDSS. (And the higher the resistance, the lower the current) . This is useful if, for example, your j113 has IDSS of 15mA but you want to use it to build an 8mA current source.
The roles of the resistor in the two circuits are different. In the Papa circuit, its chief role is to help infer the IDSS from the voltage drop across it (and its known resistance
value). In the other circuit, the resistor lowers the current to below IDSS and also allows you to calculate this adjusted current value.
EDIT: Ignore the circuit I posted and use what ZM described above. The pot does the degeneration and you use the fixed resistor for current measurement. Separating the two roles makes it easier to see what's happening.
Again, IDSS, by definition, means the current that flow when the gate and source pins are at the same voltage (which is the case if you short the two pins together).
The circuit Papa described measures IDSS., and you can use it for j113 as well. (You may want to adjust the resistor value for high IDSS parts). Incidentally, the range of Idss for j113 is quite large and the ones I've tested all have IDSS somewhat above 10mA.
The diagram I posted include a resistor between the gate and source. It does not measure IDSS. since having that resistor makes the voltage at the gate lower than that of the source and make the j113 conduct less current than IDSS. (And the higher the resistance, the lower the current) . This is useful if, for example, your j113 has IDSS of 15mA but you want to use it to build an 8mA current source.
The roles of the resistor in the two circuits are different. In the Papa circuit, its chief role is to help infer the IDSS from the voltage drop across it (and its known resistance
value). In the other circuit, the resistor lowers the current to below IDSS and also allows you to calculate this adjusted current value.
EDIT: Ignore the circuit I posted and use what ZM described above. The pot does the degeneration and you use the fixed resistor for current measurement. Separating the two roles makes it easier to see what's happening.
Last edited:
Yeah it allows for easy swapping and a tip from the creator.
See post 168 and 169. I had a similar question
https://www.diyaudio.com/community/threads/diy-biamp-6-24-crossover.357657/post-6336243
Normally you would set the J113 for 6 mA. In point of fact you can use the 6 mA 2sk170
at higher levels without issues. I have documented this elsewhere on the forum.
Thanks for all the help everyone.
I have begun testing for Idss with my little test circuit from NP, where the Gate is shorted to Source followed by a 100 ohm resistor that is connected to -9V pole on the battery. Drain goes directly to +9V pole on the battery.
Beginning with J113 I am reading around 3.16V after 30 seconds. It is pretty stable, so I guess I don't need a 470R gate stopper, whatever those are. This means my J113 has an Idss of 31.6mA +/-0.3 mA.
I guess it has no consequence for the 6-24 crossover, just for double checking. I am not going to use them all so it can be nice to pick out the ones that are matched even closer to each other.
The idea is to test everything, pick out the J113s that are closest to the median, then test the 2SK170BL and per ZM's advice (I think) pick the 2SK170 with the highest Idss, which in my case will be around 11-12mA, since I have 100 pieces of the 2SK170BL variant.
Then I will install a 200 ohm variable resistor in the position for theQ2 bias resistor on the 6-24 crossover PCB board. After powering everything up, I can dial it in so that I get the perfect current across the variable resistor. And by current I mean the voltage across the variable resistor that when dividing with, whatever resistor value I use in the variable resistor, gives me the current. So obvious!
Then I will do the same for Q1 bias resistor, even if it is less important, or not even necessary.
I am still a bit uncertain which current will be the absolute optimum current that can be measured across Q2 bias resistor and later the Q1 bias resistor.
Alternatively, I could just trust Papa, and use the J113 for Q2 and the darn 100 ohm resistors that he included in the kit for Q2 bias resistor, and then pick out the 2Sk170 that measures exactly 8mA, short the Q1 bias resistor on the 6-24 crossover PCB board, and live happily ever after.
Or was it the 2Sk170 that measured 10mA in Idss?
I have begun testing for Idss with my little test circuit from NP, where the Gate is shorted to Source followed by a 100 ohm resistor that is connected to -9V pole on the battery. Drain goes directly to +9V pole on the battery.
Beginning with J113 I am reading around 3.16V after 30 seconds. It is pretty stable, so I guess I don't need a 470R gate stopper, whatever those are. This means my J113 has an Idss of 31.6mA +/-0.3 mA.
I guess it has no consequence for the 6-24 crossover, just for double checking. I am not going to use them all so it can be nice to pick out the ones that are matched even closer to each other.
The idea is to test everything, pick out the J113s that are closest to the median, then test the 2SK170BL and per ZM's advice (I think) pick the 2SK170 with the highest Idss, which in my case will be around 11-12mA, since I have 100 pieces of the 2SK170BL variant.
Then I will install a 200 ohm variable resistor in the position for theQ2 bias resistor on the 6-24 crossover PCB board. After powering everything up, I can dial it in so that I get the perfect current across the variable resistor. And by current I mean the voltage across the variable resistor that when dividing with, whatever resistor value I use in the variable resistor, gives me the current. So obvious!
Then I will do the same for Q1 bias resistor, even if it is less important, or not even necessary.
I am still a bit uncertain which current will be the absolute optimum current that can be measured across Q2 bias resistor and later the Q1 bias resistor.
Alternatively, I could just trust Papa, and use the J113 for Q2 and the darn 100 ohm resistors that he included in the kit for Q2 bias resistor, and then pick out the 2Sk170 that measures exactly 8mA, short the Q1 bias resistor on the 6-24 crossover PCB board, and live happily ever after.
Or was it the 2Sk170 that measured 10mA in Idss?
Last edited:
I am sorry, but this comment is very interesting, yet I can’t translate it to the 6-24 crossover in my head. Is the 2SK170’s bias resistor the Gate Stopper? Meaning it should not be replaced by a shorted wire?
Edit: No, the gate stopper must the 1K resistor placed right before the JFETs.
Last edited:
gate stopper is gate series resistor, preventing that action of interelectrode capacitances transform your puny JFet in oscillator thingie
in case of matching/testing - without the same, some JFets never get to steady Iq, or (even worse/more often/likely case) they're showing inconsistency of setup contacts (one Idss while standing freely in socket, other Idss while you push it with finger/tweezers)
introducing 470R gate stopper is preventing all troubles
that's what I learned while dealing with several K's of 2SK2145BL, impressive little buggers
now, time to move on from really basic things, there is a final step of clutter which every thread can tolerate
in case of matching/testing - without the same, some JFets never get to steady Iq, or (even worse/more often/likely case) they're showing inconsistency of setup contacts (one Idss while standing freely in socket, other Idss while you push it with finger/tweezers)
introducing 470R gate stopper is preventing all troubles
that's what I learned while dealing with several K's of 2SK2145BL, impressive little buggers
now, time to move on from really basic things, there is a final step of clutter which every thread can tolerate
When you use the variable resistor to calculate the current it is just a pita. Because you will have to measure the R of the pot every time to calculate the current. Fixed R is way better for this job. If you really want to dial the J113 current sources in, just put 10R in series with the pot and measure across the fixed 10R. Downside is that the measurement device has to be precise at around 10 mV.
Trust Papa! And just make sure the Idss of the SK170 is a bit higher than the current of the CCS (J113 and 100R). Matching is not really needed here.
Trust Papa! And just make sure the Idss of the SK170 is a bit higher than the current of the CCS (J113 and 100R). Matching is not really needed here.