John Curl amp

bias:
 

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john curl said:
Bob, there is a second feedback loop that lowers the drive impedance to the output devices. Also, I would recommend higher Gm parts than you tend to use, so they will bootstrap better.


Hi John,

I was apparently looking at the wrong schematic. I was looking at the schematic in post 48 where the MOSFETs are being used. I guess I was supposed to be looking at the JC-3 schematic where the bipolar outputs are shown.

I see the pair of 1 meg feedback resistors from the VAS to the input that you are referring to. Back of the envelope, it looks like these will cause the VAS to have an output impedance of about 500 ohms. This is not as bad as I thought.

If the VAS is feeding four MOSFETs unbuffered (two pairs) and you have Cgs bootstrapping on the order of 14:1 into a 4 ohm load, it looks like the total capacitance of all four MOSFETs that the VAs will see will be on the order of about 960 pF (each MOSFET is contributing about 150 pF from Cgd and 90 pF from bootstrapped Cgs). This will corner with the 500 ohms output impedance of the Vas at about 330 kHz. this open-loop pole will move around quite a bit with signal due to the Cgd variations, but maybe it is far enough out that it will not matter much.

Not sure what the design is running the VAS idle current at, but if it is unbuffered and looking into an average total of nearly 1000 pF in the output stage, it may need to be biased at a standing current of at least 50 mA in order to meet a 100 V/us slew rate.

Cheers,
Bob
 
john curl said:
PMA, 24 ohms for R1, and 20 ohms for R7 might just do it. Also, reduce comp caps to 20pf, then 10pf. Thanks in advance.

R1 = 24 is fine. R7 = 20 results in high order harmonics to rise, I finished at R7 = 40. Caps of 10pF make stability tricky, it should be at least 15pF, I would vote for 20pF.
 

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PMA, you can go back to 20pf or even 30pf. All that I care about is that the open loop bandwidth is 20 KHz or more. The lead cap (2pf) might not be optimum, as well.
40 ohms, with these devices is OK, but I would have thought with a larger device, that the higher current would have been better.
 
John, I would finish with compcaps 20pF and FBcap 3.9pF. Please look at square response at 100kHz.

Regardless its age, it is a remarkable design between low-power amplifiers. The speed and distortion spectrum.

I would challenge those who are interested to build it, and fine tune with real-world components. Use polypropylene input cap, no mylar!
 

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So am I - thanks again. I think I actually have some of the antedeluvian devices called out for the input stage, but as has been pointed out, the modern alternatives are nicer. If you wanted to match the lower transconductance of the original JFETs, J113s and J175/J176 might work.
 
For grins, I just did a simulation using J113s and J176s for input devices, D40D7 and D41D7 for cascode transistors, directly driving IRFP240 and IRFP9240 output devices. I used a VGS multiplier to set output bias. Simulated distortion was quite good for such a simple circuit (thanks, JC). Distortion may even be better when I balance out the offset. If anyone is interested, I'll post the circut when I'm finished playing. Fets and cascode transistors were biased fairly hot, which is something I tend to do in any case.