Answers to questions:
I started the simulation with an inverting design somewhat similar to the old JC design. The objective was to see for myself if the pared-down input stage would really drive a pair of MOSFETs directly. I wanted also to see how some old, fairly low transconductance JFETs would do in the design, hence the J113 and J176. I also happen to have enough of said devices on hand so I could match up a few pairs if I wanted to test reality vs. simulation. The same was true for the D40D7 and D41D7 driver transistors. These are old GE devices no longer made, but really quite nice for the time. The TO-202 package offered the possibility of running without a heatsink. There are many modern devices that would do as well. I chose the higher voltage output MOSFETs, again, because I have them on hand.
I chose the asymmetric bias network because I have used it before with success, and it was quick and easy to draw and adjust for purpose of the simulation. I would use a polypropylene capacitor across it rather than a teflon cap, if necessary.
I added the gate resistors on the input JFETs because I have had problems with parasitic oscillation in complementary JFET input stages in the past. The resistors may not be necessary with the low transconductance devices, though they probably offer a little RFI filtering. I encountered the oscillation problem with high transconductance devices (2SJ73, 2SK146) used in a double cascode setup. This was a a cascode stage to protect the input devices, operating into a folded cascode second stage. I admit that a less slippery input stage may not have such issues. At any rate, the resistosrs can be easily jumpered out if noe needed> I use 1/8W packakes standing uo, so that the resistor body can be placed quite close to the gate with a minimum lead length between resistor and FET.
I chose fairly large resistors on the output MOSFET gates so I wouldn't have to do much messing around to squelch oscillation. I didn't try to play with the values. My main preoccupation was tinkering with the common source resistor on the input stage as well as the VGS multiplier in order to get some sensible bias currents.
When all was said and done, the original inverting incarnation of the circuit ran pretty well from the get-go, though there was a persistent 40mV of output that reqired trimming, just like in the original circuit. This bugged me a bit, as I'm routinely able to match my input FETs with enough precision to avoid the need for trimming.
With that in mind, I rearranged the circuit to non-inverting as I usually do. I generally use a feedback circuit I found in an analysis of a Nakamichi amp in Audio magazine ~30 years ago. This circuit used unity gain feedback via a high value resistor. The gain network is coupled via a relatively low value film capacitor. This arrangement made a lot of sense to me, especially with JFET or MOSFET inputs,, and I've used it pretty much exclusively since then.
The rearranged circuit still had about the same amount of offset (~40mV). Using higher transconductance devices cut down the offset to 1/4 the original value, so I would assume that this is an open loop gain issue where you need sufficient gain to counter the assymetry in VBE between the two driver transistors. I was also able to trim the offset by adjusting one of the 220 ohm load resistors on the input stage, which lends some credence to this view. As mentioned before, compensation caps were need with the higher transconductance input stage in order to squelch oscillation, just like JC said.
Some of the remaining offset with the higher transconductance input stage is probably also due to assymetric impedances on the two inputs interacting with the bias current. I encountered this problem on a JFET input amp I'm currently boxing up, and solved the problem in simulation and in practice by cascoding the input stage so that the gate to drain voltage was below the exponential knee of the gate leakage curve. This took the offset from 10mV down to sub-mv values for a pair of well matched input devices. Of course the cascode also has other beneficial effects...
All in all, the circuit proved that the input stage can drive the output FETs directly. I may build a version of it once I have about 4 other projects boxed up and out of the way.
I started the simulation with an inverting design somewhat similar to the old JC design. The objective was to see for myself if the pared-down input stage would really drive a pair of MOSFETs directly. I wanted also to see how some old, fairly low transconductance JFETs would do in the design, hence the J113 and J176. I also happen to have enough of said devices on hand so I could match up a few pairs if I wanted to test reality vs. simulation. The same was true for the D40D7 and D41D7 driver transistors. These are old GE devices no longer made, but really quite nice for the time. The TO-202 package offered the possibility of running without a heatsink. There are many modern devices that would do as well. I chose the higher voltage output MOSFETs, again, because I have them on hand.
I chose the asymmetric bias network because I have used it before with success, and it was quick and easy to draw and adjust for purpose of the simulation. I would use a polypropylene capacitor across it rather than a teflon cap, if necessary.
I added the gate resistors on the input JFETs because I have had problems with parasitic oscillation in complementary JFET input stages in the past. The resistors may not be necessary with the low transconductance devices, though they probably offer a little RFI filtering. I encountered the oscillation problem with high transconductance devices (2SJ73, 2SK146) used in a double cascode setup. This was a a cascode stage to protect the input devices, operating into a folded cascode second stage. I admit that a less slippery input stage may not have such issues. At any rate, the resistosrs can be easily jumpered out if noe needed> I use 1/8W packakes standing uo, so that the resistor body can be placed quite close to the gate with a minimum lead length between resistor and FET.
I chose fairly large resistors on the output MOSFET gates so I wouldn't have to do much messing around to squelch oscillation. I didn't try to play with the values. My main preoccupation was tinkering with the common source resistor on the input stage as well as the VGS multiplier in order to get some sensible bias currents.
When all was said and done, the original inverting incarnation of the circuit ran pretty well from the get-go, though there was a persistent 40mV of output that reqired trimming, just like in the original circuit. This bugged me a bit, as I'm routinely able to match my input FETs with enough precision to avoid the need for trimming.
With that in mind, I rearranged the circuit to non-inverting as I usually do. I generally use a feedback circuit I found in an analysis of a Nakamichi amp in Audio magazine ~30 years ago. This circuit used unity gain feedback via a high value resistor. The gain network is coupled via a relatively low value film capacitor. This arrangement made a lot of sense to me, especially with JFET or MOSFET inputs,, and I've used it pretty much exclusively since then.
The rearranged circuit still had about the same amount of offset (~40mV). Using higher transconductance devices cut down the offset to 1/4 the original value, so I would assume that this is an open loop gain issue where you need sufficient gain to counter the assymetry in VBE between the two driver transistors. I was also able to trim the offset by adjusting one of the 220 ohm load resistors on the input stage, which lends some credence to this view. As mentioned before, compensation caps were need with the higher transconductance input stage in order to squelch oscillation, just like JC said.
Some of the remaining offset with the higher transconductance input stage is probably also due to assymetric impedances on the two inputs interacting with the bias current. I encountered this problem on a JFET input amp I'm currently boxing up, and solved the problem in simulation and in practice by cascoding the input stage so that the gate to drain voltage was below the exponential knee of the gate leakage curve. This took the offset from 10mV down to sub-mv values for a pair of well matched input devices. Of course the cascode also has other beneficial effects...
All in all, the circuit proved that the input stage can drive the output FETs directly. I may build a version of it once I have about 4 other projects boxed up and out of the way.
Mr. Curl,
Inverting topologies have their merits, and I have some experience with them. They requires a good PCB routing. Without extra care when routing the PCB tracks, an inverting power amp is easier to oscilate (due to wrong PCB routing) compared to non-inverting power amp topology. I think this is because the output has already 180deg invert than the input. Input tracks should be away from output tracks anywhere in the cct.
Inverting topologies have their merits, and I have some experience with them. They requires a good PCB routing. Without extra care when routing the PCB tracks, an inverting power amp is easier to oscilate (due to wrong PCB routing) compared to non-inverting power amp topology. I think this is because the output has already 180deg invert than the input. Input tracks should be away from output tracks anywhere in the cct.
Fellow designers, let me give you my opinion and approach on amplifier design, so that my earlier comments make more sense to you.
My design guidelines are:
Complementary symmetry, and push-pull design throughout.
Direct coupling from input through output.
Fets where possible and practical.
Low negative feedback, even zero negative feedback if practical and possible.
Fast circuits, with high open loop bandwidth.
Class A, as much as practical and possible.
Regulated driver stages if possible
Servos can be very useful.
I am NOT interested in cap input, slow circuits, quaisi-complementary, feedback output pairs, or electrolytic caps in series with the feedback resistors.
I have done each and every concept, that I both like and dislike. I prefer to stick to, and be associated with the concepts that I like.
For the record, I have added output mosfets to my traditional drive stage and had it work successfully, in the past. I have made all complementary mosfet power amps, and I like balanced bridge designs for higher power, when practical and possible.
My design guidelines are:
Complementary symmetry, and push-pull design throughout.
Direct coupling from input through output.
Fets where possible and practical.
Low negative feedback, even zero negative feedback if practical and possible.
Fast circuits, with high open loop bandwidth.
Class A, as much as practical and possible.
Regulated driver stages if possible
Servos can be very useful.
I am NOT interested in cap input, slow circuits, quaisi-complementary, feedback output pairs, or electrolytic caps in series with the feedback resistors.
I have done each and every concept, that I both like and dislike. I prefer to stick to, and be associated with the concepts that I like.
For the record, I have added output mosfets to my traditional drive stage and had it work successfully, in the past. I have made all complementary mosfet power amps, and I like balanced bridge designs for higher power, when practical and possible.
We know, it is here:
http://www.parasound.com/pdfs/JCinterview.pdf
and here:
http://www.gspr.com/parasound/jc_6_points.html
http://www.parasound.com/pdfs/JCinterview.pdf
and here:
http://www.gspr.com/parasound/jc_6_points.html
John,
I know your preferences and design philosophy. I wonder if you would allow me to post 2 recent measurements done on an amp with symmetrical CFB output stage biased at 1.5A, out of global NFB. The amp is rated at 33W/8 ohm and 60W/4 ohm, similar as JC3 discussed now. The 1st image is for 8W/8 ohm:
I know your preferences and design philosophy. I wonder if you would allow me to post 2 recent measurements done on an amp with symmetrical CFB output stage biased at 1.5A, out of global NFB. The amp is rated at 33W/8 ohm and 60W/4 ohm, similar as JC3 discussed now. The 1st image is for 8W/8 ohm:
Attachments
john curl said:
I would love to find these or a suggestion for an alternative. It seems impossible to build anything with with FETs these days.
Is there a source for the Toshiba's or any predictable alternative? Is Erno the only source? He doesn't appear to list the 389/109bl's anymore.
Regards, Mike.