The added 10 ohm resistors were to current limit the driver devices in case the amp was shorted. The original output transistors, in parallel could peak almost 50A, so they could tolerate a momentary short, but the undersized, but fast, driver devices needed to be limited to 2A.
No cap is apparently necessary across the bias stage, for some reason. Maybe, because it works that way as well.
No cap is apparently necessary across the bias stage, for some reason. Maybe, because it works that way as well.
Attached is a schematic for a symmetric folded cascode stage driving complementary MOSFETs directly, as mentioned by JC a few posts earlier. A VGS multiplier was used to set bias. I used the D40D7 ahd D41D7 TO-202 devices for VAS transistors as they are fast and the models were readily available in PSpice. The TO-202 package has 75C junction to ambient thermal resistance, so it can handle a few tens of milliamperes at 20V. I used J113 and J174 for input devices. The input was arranged as non-inverting, but inverting also worked. With the relatively low transconductance of the input stage, no compensation was required. When 2SJ74 and 2SK170 were substituted in the imput stage, compensation caps (22p) were required at the VAS stage to squelch oscillation.
Attachments
This is an interesting design, but it deviates from my course in several ways. First, why cap input? Second, why starve the output fets? Third, why add 100 ohm resistors at the input of the jfets? Fourth, why change the bias track to an unsymmetrical type and adding a 1uF cap across it? Do you know the price and size of 1 uF Teflon caps? 
Also, why 200V fets? How about 60V or 100V fets? Why 330 ohms, why not less than 100 ohms?
Also, why 200V fets? How about 60V or 100V fets? Why 330 ohms, why not less than 100 ohms?
Jfets do NOT need input resistors. However, this design could use an RFI filter/impedance defining R-C resistor input of 100 ohms and 100pf on the very input.
I chose inverting topology for the JC-3 to LOWER common mode distortion. With cascode devices on the input, this recent design will suffer from common mode distortion. Just another potential compromise.
I chose inverting topology for the JC-3 to LOWER common mode distortion. With cascode devices on the input, this recent design will suffer from common mode distortion. Just another potential compromise.
It should be said, also, that this design started as a tweeter amp design in a tri amplified system. The tweeter had an efficiency of 108spl/watt. 10W was more than enough, and the input cap could be made very small to limit any low frequency input.
Later, this design was slightly improved and given to Mark Levinson as a small amp design. I was never paid for this design, so I published it many years later.
Later, this design was slightly improved and given to Mark Levinson as a small amp design. I was never paid for this design, so I published it many years later.
One of the nice things about JFET inputs, besides sound quality, is you don't need input coupling caps.john curl said:This is an interesting design, but it deviates from my course in several ways. First, why cap input? Second, why starve the output fets? Third, why add 100 ohm resistors at the input of the jfets? Fourth, why change the bias track to an unsymmetrical type and adding a 1uF cap across it? Do you know the price and size of 1 uF Teflon caps?
Also in John's design the gate leakage currrents cancel each other.
Cheapest Teflon I could find in 1µF is the Solen from Partsconnexion for $64.85:
http://www.partsconnexion.com/catalog/CapacitorsFilm.html
Or one must // two Russian 0.47µF , but they are HUGE!
Hi Wrenchone,
I do not think Q3 (or Q4) could be considered as a folded cascode.
It is a standard voltage driven common emitter by the potential difference across the voltage across R2 and R3 (or R4 and R5), its base is not at a fixed potential referenced to power supply voltage, ground neither J1 and J2 (J3 and J4) sources node.
I do not think Q3 (or Q4) could be considered as a folded cascode.
It is a standard voltage driven common emitter by the potential difference across the voltage across R2 and R3 (or R4 and R5), its base is not at a fixed potential referenced to power supply voltage, ground neither J1 and J2 (J3 and J4) sources node.