Realistic DAC PSU decoupling capacitor simulation model ...

In addition IME diyiggy is once again right. Some trace length between regulator and clocks helps, at least if using Crystek 957 and 805 film decoupling caps.
It is quite possible diyiggy was right. However this follows a common theme: outlandish claims are never accompanied by measurements. Only subjective sighted listening without even any A/B comparison.
 
Yep, sure, but two caps to try will not break the bank if you have already the tools to do it...I haven't. Just hope this is replicable for people that can not affoard expensive clocks but having the Crystek as it worked for me.

Let come back to the topic of gentlevoice please after that outland exursion...
 
Yes that's the point, it's an inductor with dissipative properties. It keeps out the noise coming in from the supply, and keeps the noise generated by the load from contaminating the main supply.

They're very often used in RF too.

Averaged over one clock period, a clock oscillator draws constant current. It doesn't need low power supply impedance at low to mid frequencies. But it needs low impedance at HF, which is provided by the local cap. You have to sim the whole network and tweak it until you get the impedance you want. Sometimes a resistor is needed in series with the bead to prevent ringing.

But if you have a load that draws variable current and needs low power supply impedance, then of course you shouldn't put the ferrite bead there. If you use a local LDO you can put it (and the pi filter) before the LDO. If you use a shunt regulator you can put a pi filter in the current source supply.
hi peufeu,
all your explainations & research work is based on LTspice only ?
do you perform some measurements to check the "conclusions" of LTspice ?

By the way, are fan of MLCC "X" type ? I guess not when I read your post. I think you should have a try...
Rgds