Understood, but it adds to the overall cost was my point. One could say the same about all the stacks of Iancanada boards that people put together.
EDIT: the other thing I would say is this sort of construction is fine for experimenting. Experimenting and prototyping is necessary in order to see what works, what doesn't, what kind of sound you can get, and figure out what you want to do if you were going to turn it into a product. But if you want to make, say, 1000 dacs to sell then you probably need to integrate more to get manufacturing costs down. That's all.
Otherwise the alternative would be to design on paper, build, test, and sell. Whether or not you do that depends are the target market. If you want to push the boundaries a little and see if you can get a little better sound than the other guy, then you may have do some extra R&D work.
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Putting two and two together, I think I understand why Andrea uses uniform weighting over number of taps that is a relatively large integer power of two, even though he could make any positive integer number with his single flip-flops.
Apparently his RTZ logic uses the master clock rather than the bit clock or the doubled bit clock. That also means that the tap-to-tap delay of the FIRDAC will be independent of the DSD rate. To get a notch at 1.4112 MHz and suppress the idle tones around fs/2 of DSD64, you need only four taps when you clock the shift register with twice the DSD64 bit clock, but you need 32 taps at 45.1584 MHz.
This also means that when my DAC is driven from Andrea's RTZ circuit, it will only suppress idle tones around fs/2 at the highest DSD rate. That is, one quarter of the master clock is where the lowest notch will be, no matter what DSD rate is used. This can work fine as long as there is nothing mixing the unsuppressed idle tones at lower DSD rates into the audio band.
OK, so the DAC isn't driven by a bit clock that comes straight out of an FPGA, but rather by a flip-flop on a reclocking board, and the data going into that flip-flop come from the FPGA. Thanks, that makes sense.
The clock used is Sine output type. Cannot go directly into JL Sounds. Andrea’s FIFO board has also a sine-square converter circuit. So I guess why Mark is using it this way. I don’t see what benefits the FIFO brings to a Synchronous system
Hans,
Probably we can work around any issue like that although it might be a little inconvenient. For DSD128 or less I could probably continue to use the reclocked BCLK. For DSD256 I would probably have to switch over to using MCLK for BCLK. Have to talk it over with Andrea to see what is possible.
Mark
BTW, I have separate squaring boards if I want to use them. The thing is JL Sounds is reclocked in a CLPD and the overall EMI/RFI isolation is not as good as I can get from going through Andrea's FIFO board. So there are probably going to be tradeoffs in any case. Give me some time to discuss with Andrea and to think about it some more. There's no rush.
I was thinking more like this separate squarer from Andrea is one of his earlier creation for diy use. The phase noise plots seem to indicate that there is loss of overall quality after conversion. The one on the FIFO board, the manual indicates a premium version i.e. hardly any loss as claimed. Also, you will need a clock doubler to go into JLSounds. I am happy with your current arrangement, just ignore the FIFO effects for now…
I have two different types of squarers from Andrea, including what I believe to be a premium one. He measures the designs for phase noise and I think they are all pretty good compared to what you might get out of Crystek, NDK SDA, Accusilicon, etc. (although the old obsolete one no longer offered turned out to be able to self-oscillate from all the gain if no clock signal was input; new ones don't have that quirk). Also, IIUC correctly the current line of diy stuff he is offering is mostly what is termed the 'lite series.' The simple squarers may come under that classification. Again IIUC, the plan was always to learn by going through successive iterations of designs. Since there is no exact end point defined right now that I am aware of, from time to time what has been developed has been offered for GB. I see no problem with that, myself. The same could be said of Iancanada and all the versions of FIFO_Pi.
OTOH, your very expensive clocks are quite good, SOA for sure, but you don't have a line of squarer's that I know of, so Andrea is probably the best source right now. Since they are still very good, I don't think it likely they are going to make Marcel's dac sound worse. Do you? Especially since there are may be a few other unturned stones in the dac to be found yet. Worrying too much about very finest clocking possible by anyone today may be getting a bit ahead of ourselves, seems to me anyway.
OTOH, your very expensive clocks are quite good, SOA for sure, but you don't have a line of squarer's that I know of, so Andrea is probably the best source right now. Since they are still very good, I don't think it likely they are going to make Marcel's dac sound worse. Do you? Especially since there are may be a few other unturned stones in the dac to be found yet. Worrying too much about very finest clocking possible by anyone today may be getting a bit ahead of ourselves, seems to me anyway.
I am happy to hear that there is a premium standalone version of the squarer. Just trying to keep the playing fields level when you switch around especially with clocks - as going into the DUT. Wanted to avoid the case where JLSounds did not sound great on its own compared with going through the FIFO although they are both driven the same source Clocks. Yes, just proceed if convenient with your plans.
Actually, just wondering with this FIFO/reclocker in place isolating timing domains, swap JLSounds with Amanero and see?
Actually, just wondering with this FIFO/reclocker in place isolating timing domains, swap JLSounds with Amanero and see?
Already have done that type of thing and much more. No point in repeating it all here.
However, its less of a question about Marcel's dac and taking a look at it, and maybe more about Andrea's designs.
Here is my short reply about in that case: Andrea makes boards that do a good job of galvanic isolation and reclocking. He does not sell or make radiated EMI/RFI shielding products. What I have found as I keep working on exposing more low level musical information and reducing things like blurred sound, is that at some point radiated EMI/RFI inside the dac box tends to become a bigger relative remaining problem. In short, radiated noise can jump round around galvanic isolation and reclocking if you let it.
Right now the radiated EMI/RFI issues are under pretty good control due to a variety of measures. Its something we could talk about at some point, but it might be kind of a digression at the moment in terms of doing more things with the DUT here right now.
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Good point Mark, I didn’t realise this limitation with JLSounds reclocking in CPLD instead of separate F/Fs. In that just forget about clocking JLSounds with OCXO. What you have Andrea’s reclocker looks much better to me
Decided to install some u.fl connectors on Marcel's dac dac. They will allow connections to the clock and data lines going to the shift registers. First they will be used to capture scope traces of the existing signals. After that the existing drive circuitry will be disconnected by removing the series termination resistors. External clock and data signals can the then be introduced through the u.fl connectors. Part of the reason for doing it this way is to make it reasonably easy to undo the changes and revert to original operation. Also probably better to have connectors on the board rather than delicate, small coax pigtails hanging off. Downside is that installing connectors is a bit tedious, and for me it requires working under the microscope. Probably ready to try playing SACD rips (DSD64) with reclocked BCLK before too much longer.