Return-to-zero shift register FIRDAC

Member
Joined 2007
Paid Member
Hi again, Marcel.

I hope this will reach you before you consider the rest of my previous post in too much detail .. I have come to think of that I should be able to just make a small trial of the lower-most FF circuitry I asked you about (and then I can also check timing etc.) so I will do that - which also means that you do not have to reply further to my previous post.

Cheers, Jesper
 
In pcm2dsd for 44k1 and 48k there's the same code. So if it works for 48k, it must work for 44k1...
I did some testing and found out more about the issue. My RTZ board reclocks DCLK with 2 flipflops (74LVC1G79). For some reason with pcm2dsd_v3 reclocking fails (no output from flipflops) at 44k1 (DCLK 11.2896MHz). It works fine at 48k (DCLK 12.288MHz). And I have no reclocking issues at either sample rate with the firmware by @xx3stksm. So my guess is that something is different in pcm2dsd_v3 regarding DCLK timing at 44k1.
 
The caveat might be the functionality of the FF handling the RTZ of the DSD DATA stream (the lower-most FF just above the XOR doubler, functional table attached). Here I use the preset & clear functionality of this lower-most LVC1G74 to clear the outputs of the DSD_DATA FFs every time the incoming DSD_CLK goes "low". That is: when the DSD_CLK goes low, _PR on the lower-most FF goes low a couple of ns later which causes a "0" on its Qnot output. This in turn "sets" a "0" on the Q outputs of all of the FFs handling the data to the LV574 output FFs. This is intended ... So far, so good.

Following this, however, the lower-most FF's _CLR is also pulled to "0" which causes both of this FF's outputs to go "high". This is also fine - maybe except for this double-"high" state not being stable. Thus, when the DSD_CLK again goes "high", according to the datasheet it will first pull _PR to "high" (this will leave Qnot on "high" as per the datasheet). When both _PR and _CLR are returned to "high" this lower-most FF is not again able to react to a clock pulse - except that both its data and clock input are grounded.

Now, the caveat to this design might be that although according to the data sheet it should work I do not know if this lower-most FF when going through this cycle may exhibit some kind of "unforeseen behavior". Might one of you know about this? Does it seem plausible that it will work?

Yes, at least I don't see any reason why this flip-flop pulse former wouldn't work. By the way, the reset inputs of the left flip-flops aren't connected yet. I haven't calculated whether the timing of the whole circuit fits, nor do I intend to.
 
Member
Joined 2007
Paid Member
@marcel:

Yes, at least I don't see any reason why this flip-flop pulse former wouldn't work.

Oh, you replied to this anyway - well thanks for considering, then ... As it is I tested this yesterday evening, and it actually does work as intended.

By the way, the reset inputs of the left flip-flops aren't connected yet.

You are right - I also noticed this last evening when I looked at the circuitry again. Somehow errors have a tendency to sneak in in the oddest of places ...
:tilt:

I haven't calculated whether the timing of the whole circuit fits, nor do I intend to.

Entirely fine, Marcel ... (incidentally, I wouldn't have asked you about this either) ...

Best wishes, Jesper
 
Another RTZ DAC lives! This is built 'out of the box' and uses a PCM2DSD module on its input. It's a breadboard build using parts assembled by @Cestrian and myself and will be given to a mutual friend in the new Year.
Yesterday I took a journey up to Yorkshire, England, to deliver the breadboard build to its new owner; he and his wife were immediately taken with the improvement over their existing Musical Fidelity DAC, commenting on how natural sounding the RTZ is, not at all 'digital' in its signature, so we have another RTZ advocate...

So it's over to him now to do as he pleases with it in terms of tweaks and aesthetics.
 
  • Like
Reactions: 2 users
I did some testing and found out more about the issue. My RTZ board reclocks DCLK with 2 flipflops (74LVC1G79). For some reason with pcm2dsd_v3 reclocking fails (no output from flipflops) at 44k1 (DCLK 11.2896MHz). It works fine at 48k (DCLK 12.288MHz). And I have no reclocking issues at either sample rate with the firmware by @xx3stksm. So my guess is that something is different in pcm2dsd_v3 regarding DCLK timing at 44k1.
I believe this issue was related to MCK/DCLK timings violating flipflop setup or hold times. Pjotr25 made me a new FW version where ODDR2 primitives were left out and this solved the problem for me. Also the channels were swapped (in my RTZ and AK4493) so Pjotr25 made another version whigh corrected the channel mappings. Now it works ok.

Here is 1k -3dBFS at 88.2kHz (ADC at 44k1).

pcm2dsd_004_2_88k2_-3dBFS.JPG
 
I would just mention than PCM2DSD (the FPGA-based Simple DSD Converter) has 4dB of attenuation rather than the 6dB standard. The standard is to limit the modulator from going to excessive limits. The standard also allows for an additional few dB of attenuation which is optional. Some extra attenuation might be used to help with tolerance to intersample overs, for example.

In the case of PCM2DSD, the 4dB of attenuation works well for hi-res, but not always as well for CDs that are pushed to the limits or above due to the loudness wars. In that case its good to provide some additional attenuation to the PCM before going into the modulator.

Since I often use PlayPCMWin to play PCM and or DSD files, I only have 3 possible attenuation settings for PCM. There is one that sounds the best, which is -6.02dB. Its not that I really need that much attenuation, its that a 6.02dB attenuation is a divide by two operation, which means it can be implemented as a bit shift rather than a more complex mathematical operation. Thus it tends to give a result that is more or less like what might be considered bit-perfect. IOW, the bit pattern remains the same, it is only shifted.

BTW, the reason I am using PlayPCMWin instead of foobar2000 is because I found out the latter introduces some distortion. Don't use that app any more.
 
Last edited:
  • Like
Reactions: 1 user
Presently I am using a SE Andrea Mori DSD dac as my main dac. Andrea has designed a discrete output stage board for it which IMHO sounds pretty darn good. There is also a power supply board for the output stage, and he makes another board to hold the power transformers for it. Its potentially a lot of stuff, although I am using my own power supplies and transformers. Could be the output stage would work with Marcel's dac. Probably have to ask Andrea about it.

Regarding the passive filter and DC removal that I have used, it relies in part the input transformers for my line amp for complete removal of RF. Regarding the filter itself, it may be a matter if trial and error to figure out what sounds best. Its not necessarily going to be silmic and or particular film caps. Usually the film bypass caps need to be quite small (~ .01uf) and they need to chosen to give a sound consistent with that of the electrolytic. By itself, its more of a DC blocking circuit with a small amount of EQ. There is still RF to integrate out, and it looks like Cestrian is also using transformers as a part of his circuitry.

EDIT: As an aside, from looking at the pic of Cestrian's dac, it appears the dac is using a shared ground for all the dac power supplies, +-15v and +5. As I explained when I was chronicling improvements to Marcel's dac by changing its surroundings, shared grounded of power supplies is one of the more harmful things that can be done when using off-board power supplies. Each of the three power supplies should be isolated from each other, with the grounds connected only at the load PCB. Otherwise there will digital crosstalk noise on every power rail at the dac board. IME any filter caps on the dac board typically do not fully mitigate the problem.

Similarly, using an Amanero without galvanic isolation (if anyone is), would be asking for ground loop troubles.

EDIT 2: IIRC, IME with Marcel's dac it was when I broke the final ground loop, the USB input ground, that SQ made a substantial improvement. Think I said it seemed like about 90-95% of the distortion/noise suddenly went away.
 
Last edited:
it appears he is using a shared ground for all the dac power supplies
Yes, the grounds aren't starred to the DAC ground pin. I can easily make a test on one of my DACs and compare as they are both wired the same way and more of less the same layout.

Edit:
Having said that, this photo was prior to me splitting the +/-15v for the filter and DAC so in that case those grounds are now starred to the DAC ground pin. However the supplies to the DAC pcb are still using the shared ground line.
 
Last edited:
Big thanks to Cestrian for sending me Marcels dac to try
I've got AYA2 and TP Buffalo32s , BIII to compare against , other dacs I've tried I no longer have.
I'll add pics later but so far Marcels dac is all just lashed up whilst I'm testing, trying tweaks etc .
I'm using shunt regs for the +/-15v and 5v , separate transformers separate ground wires running to dac board . I'm using Amanero into pcm2dsd module .
Listening to it SE I found the sound was very good although it seemed a little flat and compressed , I've tried removing L1 on the Amanero , added another shunt reg PSU and run both the pcm2dsd and Amanero . This made a nice improvement especially in the highs more space around instruments and vocals .

Next thing was changing the NE5532's for U5,6,12 and 13 to OPA1678 's , this to my ears made quite a difference to the sound . It sounds noticeably more open less compressed with better attack . Anybody building this dac I'd highly recommend choosing the OPA1678's over those 5532's .

I'd like to try running disconnecting the last stage and coupling caps next, maybe try running wires from the input pads of C14 and 40 to output sockets , I'll add 56R in series its the nearest value

Also thanks again to Marcel and everybody else thats contributed to the thread , I look forward to trying more things with this dac and hoping to see others updates
 
Nice to see someone else trying some things with Marcel's RTZ dac. Please do post some pics and keep us apprised of your other experiments. IME bypassing the last section of the output stage board makes for a significant difference. What I did was cut a few traces and add some jumper wires. That way the output stage can pretty easily be restored to it original state if desired. The other nice mod on the output board is to reduce the bandwidth of the differential summing stage so that it only acts as a DC servo. Sure sounded better to me is SE after doing that. Also, I hope you are running the output stage from separate power supplies, instead of sharing the power supplies for the dac board. Otherwise there is digital junk on the output stage rails that affects the sound.

In addition I would also suggest to save the shunt regulators for the output stage and for the dac board Vref. Amanero and PCM2DSD can run from 7805 regulators and work fine. Also for series pass regulators, loading down the output with a resistor to ground can sometimes improve their performance. Its one of those things where you just have to try it and see. For my 3.3v regulators I might go as low as 47R to ground. OTOH for Marcel's Vref I paralleled 120R with each of the four 22uf X5R shift register bypass caps. That did help some too.
 
Last edited:
  • Like
Reactions: 1 user