Nice work. It will be interesting to see how they compare measurement wise and sound wise. What sort of RTZ scheme did you use?
TCD
.. how can you leave us without a photo ? [emoji846]
Nonetheless... I am really curious to hear your findings
In order to make it works have you doubled the clocks ?
Maybe a dumb question but how do you attenuate the signal in this configuration ?
I mean i don't build the dsc dac yet, but i am thinking of it, and in my case i need to build something "complete" including the volume control.
From what i understand the whole point of this project is to replace hqplayer that also seems to be the only thing working to attenuate the dsd signal, it's what i want, i'd prefer build a complete and "standalone" unit. The star pure dsd is attractive in that regards with it's lcd screen.
So either i use an analog pre after the dsc, or i need some kind of dsp between the amanero and modulator, like a minishark... but it's very expensive, also seems over the top for this use, and i don't know how it would work with the few native dsd i own.
I mean i don't build the dsc dac yet, but i am thinking of it, and in my case i need to build something "complete" including the volume control.
From what i understand the whole point of this project is to replace hqplayer that also seems to be the only thing working to attenuate the dsd signal, it's what i want, i'd prefer build a complete and "standalone" unit. The star pure dsd is attractive in that regards with it's lcd screen.
So either i use an analog pre after the dsc, or i need some kind of dsp between the amanero and modulator, like a minishark... but it's very expensive, also seems over the top for this use, and i don't know how it would work with the few native dsd i own.
Possible but not extremely convenient especially if you chain is balanced, i think i will find myself a nice preamp with remote control, i still have a bruno putzey's preamp somewhere...
Anyway i have a few questions.
I have a cronus / hermes for bbb boards i don't use. Will it work with this chain BBB - Hermes - Cronus with 22/24 oscillators - DSD modulator - DSC2. I red the previous post of the thread but i don't understand much this history of mute.
Also a quick search of the Xilinx programming cable reveal it's expensive (around 250€). There is copy on chinese market for very cheap (~20€). Anyone have experience with them ?
Anyway i have a few questions.
I have a cronus / hermes for bbb boards i don't use. Will it work with this chain BBB - Hermes - Cronus with 22/24 oscillators - DSD modulator - DSC2. I red the previous post of the thread but i don't understand much this history of mute.
Also a quick search of the Xilinx programming cable reveal it's expensive (around 250€). There is copy on chinese market for very cheap (~20€). Anyone have experience with them ?
Ok thank you for your feedback, a shame really to get this only to use it once... but i guess there is no choice. I know i am boring 
I'd really like to try this and the dsc2, looks like a fun project and a friend electronics offer me to help soldering the xilinx fpga that is apparently very hard to solder without pro machinery.
I looked at different prototype pcb maker and build a single pcb is really expensive for a 4 layer, around 100 euros. A shame chientechnical don't answer my solicitation, i suppose i am very late to this. Anyway i am a taker if someone has a pcb (or fully assembled) to sell for this and the dsc 2.5.2.
I'd really like to try this and the dsc2, looks like a fun project and a friend electronics offer me to help soldering the xilinx fpga that is apparently very hard to solder without pro machinery.
I looked at different prototype pcb maker and build a single pcb is really expensive for a 4 layer, around 100 euros. A shame chientechnical don't answer my solicitation, i suppose i am very late to this. Anyway i am a taker if someone has a pcb (or fully assembled) to sell for this and the dsc 2.5.2.
Some guys built Xilinx Virtual Cable by writing a progam to run with FT232 chip or with Raspberry Pi:
https:Branches * tmbinc/xvcd * GitHub
FPGA usually uses a standard 24family or 25family EEPROM. You can directly program them with a cheap EEPROM programmer with an extension cable for in-system writing. I guess you need a bin file instead of MCS. I haven't experienced writing with an extension cable, but it works fine. The problem is they often sell a defective product, 1 out of 2 in my experience.
CH341a BIOS Programmer 24 25 Series EEPROM Flash USB Module | Laptop and Desktop | eBay
CH341a BIOS Programmer 24 25 Series EEPROM Flash USB Module | Laptop and Desktop | eBay
The device driver and programming software for CH341a are a bit tricky. The one I have succeeded in is this.
Releases * nofeletru/UsbAsp-flash * GitHub
This is the BIOS reflash of the laptop PC by CH341a.
BIOS or SPI programming on Windows or Linux using a CH341a MiniProgrammer | Jensd's I/O buffer
Releases * nofeletru/UsbAsp-flash * GitHub
This is the BIOS reflash of the laptop PC by CH341a.
BIOS or SPI programming on Windows or Linux using a CH341a MiniProgrammer | Jensd's I/O buffer
I have been succesfuly using this tool for writing directly on flash device on XMOS USB to I2S boards. Xmos also provides a comand line tool to transform proprietary firmware extension .xe file into a .bin file. I have no any experience with Xilinx FPGA, but as I have read it is possible to generate .bin file (i.e. from .bit file) using PROMGen command line tool.
Thanks @olo111 & @PJotr25 for sharing this project and also @xx3stksm for sharing his work.
Actually, xx3stksm's bit versions are more suitable for my project, because they are more "timing friendly". I use a modified version of USB2I2S, and clock domain selectror CPLD pins also enable/disable the appropiate power supply (each oscillator has its own PS). There is too much time spent for the PS to reach its designed voltage, at every SR domain change, so the FPGA receives the input signals too late (?) and its oput stream breaks in case of olo@PJotr bit version. Anyway, I have tested it with a regular Amanero board, and it works great too.
Actually, xx3stksm's bit versions are more suitable for my project, because they are more "timing friendly". I use a modified version of USB2I2S, and clock domain selectror CPLD pins also enable/disable the appropiate power supply (each oscillator has its own PS). There is too much time spent for the PS to reach its designed voltage, at every SR domain change, so the FPGA receives the input signals too late (?) and its oput stream breaks in case of olo@PJotr bit version. Anyway, I have tested it with a regular Amanero board, and it works great too.
Attachments
Thanks for your feedback. My old DAC with FPGA-based DSM accepted both sample rates(44k family and 48k family). I probably asserted internal reset to ensure proper operation of PLL inside FPGA. I remember it takes about 0.3 seconds to output flawless sound. My bit file itself still has the internal reset function as long as I checked the original schematic. However, it is pulled up to ignore the internal reset because your microcontroller doesn't have I/O to enable the pin. No reset has no problem if your PCB has continuous sound. It's only for your reference.
By the way, I have been hacking my FPGA-based 1bitDSM DAC. One primary staff is multibit DSMed 1bit DAC like Mola Mola. Multibit DSM itself(4 values or 6 values) is easy to implement because 1bit(2 values) and multibit have a slight difference if your module is done by hardware. The problem is your analog section. Multibit DSMed 1bit means a higher clock rate; 128OSR with 4 values results in 128x3=384OSR(6.144x3=18.432MHz). If your analog section is good at a high clock rate, the advantages can outperform the disadvantage. The advantages are large max amplitude(probably +2dB in 5th order) and high stability at small amplitude(usually from -30dBFS to -60dBFS). If I can successfully implement that module into xc6slx9, I will post a bit file. But I'm not sure if the advantages can outperform the disadvantage because my analog section failed to make the most of it. The disadvantage was, unfortunately, larger than the advantages.
By the way, I have been hacking my FPGA-based 1bitDSM DAC. One primary staff is multibit DSMed 1bit DAC like Mola Mola. Multibit DSM itself(4 values or 6 values) is easy to implement because 1bit(2 values) and multibit have a slight difference if your module is done by hardware. The problem is your analog section. Multibit DSMed 1bit means a higher clock rate; 128OSR with 4 values results in 128x3=384OSR(6.144x3=18.432MHz). If your analog section is good at a high clock rate, the advantages can outperform the disadvantage. The advantages are large max amplitude(probably +2dB in 5th order) and high stability at small amplitude(usually from -30dBFS to -60dBFS). If I can successfully implement that module into xc6slx9, I will post a bit file
. But I'm not sure if the advantages can outperform the disadvantage because my analog section failed to make the most of it. The disadvantage was, unfortunately, larger than the advantages.
Thanks for your feedback. My old DAC with FPGA-based DSM accepted both sample rates(44k family and 48k family). I probably asserted internal reset to ensure proper operation of PLL inside FPGA. I remember it takes about 0.3 seconds to output flawless sound. My bit file itself still has the internal reset function as long as I checked the original schematic. However, it is pulled up to ignore the internal reset because your microcontroller doesn't have I/O to enable the pin. No reset has no problem if your PCB has continuous sound. It's only for your reference.
By the way, I have been hacking my FPGA-based 1bitDSM DAC. One primary staff is multibit DSMed 1bit DAC like Mola Mola. Multibit DSM itself(4 values or 6 values) is easy to implement because 1bit(2 values) and multibit have a slight difference if your module is done by hardware. The problem is your analog section. Multibit DSMed 1bit means a higher clock rate; 128OSR with 4 values results in 128x3=384OSR(6.144x3=18.432MHz). If your analog section is good at a high clock rate, the advantages can outperform the disadvantage. The advantages are large max amplitude(probably +2dB in 5th order) and high stability at small amplitude(usually from -30dBFS to -60dBFS). If I can successfully implement that module into xc6slx9, I will post a bit file
From memory your analog stages could possibly be improved IMO. There was
voltage swing on all the current switches and moving to a virtual GND I-V
type arrangement would alleviate this.
TCD
Perfect if the FPGA itself select the 44.1/48Khz family and itself Mute function both.
What the Pin of FPGA in your bit file used for select 44.1K/48K family. Can you provide schematic!? We're can wire manual on the pin of FPGA for try.
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FPGA can't detect family change(44k to 48k or 48k to 44k) because it doesn't include an independent oscillator. It's only the microcontroller that can detect and control FPGA registers. When family change occurs, the best scenario is asserting MUTE(pin118) and reset PLL inside FPGA after successful oscillator change. My old DAC oscillator probably took 0.3 seconds for family change. PLL relock is so fast that the total muting time was 0.4 seconds(0.1 seconds for PLL relock). If you are unlucky, you need to do that to ensure PLL stability. As far as you don't have a problem, you don't need PLL reset. Accessing FPGA registers is also not easy.
Whether you can succeed PWMed 1bit DSM or not depends on your analog section(pulse train to analog conversion). Mola mola claims they employ 5bit 7th order 64OSR and convert it to a high rate pulse train(3.072x32=98.304MHz). I can't even imagine why such a high clock results in a clean analog signal(more than 120dB THD+N). If I dare to try PWMed 1bit DSM, 640OSR(6.144x5=30.72MHz) is the max. But I'm sure some new architecture for a high clock rate is mandatory for the analog section. It's not easy.
WRT Mola Mola, I think you might find 98.304 MHz is referring to the master
clock and the actual pulse train (RTZ) is likely 1/4 of that = 24.576 MHz.
I can't even imagine why such a high clock results in a clean analog signal(more than 120dB THD+N). If I dare to try PWMed 1bit DSM, 640OSR(6.144x5=30.72MHz) is the max. But I'm sure some new architecture for a high clock rate is mandatory for the analog section. It's not easy.
As I stated your analog stages with differential current steering look mainly
pretty good but they should feed a virtual ground which will take out signal
related voltage swing non linearities.
TCD