Regarding cascoding: the only result of cascode added to M1 and M2 is a non-trivial stability problem. It does not change distortion at all. To solve stability, Vdg capacitances must be added. This results in lower slew rate.
So, cascoding has 2 results in this circuit:
1) reduced slew rate (sorry, I do not want this)
2) reduced VAS voltage swing
IMO, it makes no sense to cascode the folded M1 and M2.
So, cascoding has 2 results in this circuit:
1) reduced slew rate (sorry, I do not want this)
2) reduced VAS voltage swing
IMO, it makes no sense to cascode the folded M1 and M2.
. Thanks for clarification. Keep up your good work
This design already has Borbely-like folded cascodes (M1, M2) and works very well with them. For some reason, I was suggested here to put additional cascodes on M1, M2; and posters suggested lower distortion of such circuit. My answer is that distortion would be about same as is now, but stability would suffer and the cure of stability would result in low slew rate (like 15-20 V/us instead of more than 60V/us we are having now /in fact 90V/us/). Why should I fulfill such suggestions?
Pavel,
I don't see why you should fulfill ANY suggestions..... your design is your design, no one else takes blame or credit, there is no expectation, and you give it here freely.
I agree emphatically with your cascode comments, and I laugh at your '...I just want it' comment. I certainly do not agree with everything you say, but it is nice to hear some real humanity.....
Hugh
I don't see why you should fulfill ANY suggestions..... your design is your design, no one else takes blame or credit, there is no expectation, and you give it here freely.
I agree emphatically with your cascode comments, and I laugh at your '...I just want it' comment. I certainly do not agree with everything you say, but it is nice to hear some real humanity.....
Hugh
Hitachi TO-220 lateral mosfet
Hi PMA,
a little off the subject but taking advantage that you use mosfets as a folded cascode in your simulations, I wonder if the models of the Hitachi (2SJ79/2SK216) listed in MicroCap software that you use are good. I do not expect them to be perfect, of course, but at least if these models do well, because I got some models the net to use in OrCad and they didn´t work.
regards
eD
Hi PMA,
a little off the subject but taking advantage that you use mosfets as a folded cascode in your simulations, I wonder if the models of the Hitachi (2SJ79/2SK216) listed in MicroCap software that you use are good. I do not expect them to be perfect, of course, but at least if these models do well, because I got some models the net to use in OrCad and they didn´t work.
regards
eD
Frankly, if it were me, I would stick with what works. You're way more experienced at this than me, so I'm merely hoping to learn something. My question was more about if the drop in performance was due to topology or parts selection.
I noticed that the VAS is biased for 15mA. Could you please provide some insight into why that level of bias is required, or perhaps this value was arrived at empirically?
I ask this because I'm considering using a Borbely derived front-end with a triple EF output stage, somewhat similar to your design presented here. But, I'm unsure how much current the VAS really needs to supply. Again, just hoping to learn.
Thanks!
I hope it is based both on experience and theory.
The higher VAS current yields higher current to charge component's and circuit capacitances. And not only VAS current, also input JFET stage current. Thus, you may get high slew rate. Compare this to conventional low current VAS, low input stage CCS + Cdom and you get the answer why some topologies are pretty slow. The higher VAS current means higher power loss on VAS devices, for sure. The 15mA is not any strict value, I would say go at least 10mA. The more, the better, but check device power and size.
Regarding empirical results - yes, I evaluted this during development of my latest preamplifier.
Regards,
15mA is an idle (bias) current. You get more AC current but at the expense of rising distortion.
But, you can easily increase the VAS bias current by increasing R5 and R7. These resistors always to be tuned individually, according to Idss of the JFETs used. Do not forget to heatsink VAS transistors if you go high VAS bias current.
Andrew,
you would find the VAS transistors used here:
PA2 power amplifier
They would withstand 100mA without any problem, just small heatsink needed.
Regards,
you would find the VAS transistors used here:
PA2 power amplifier
They would withstand 100mA without any problem, just small heatsink needed.
Regards,
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