Maybe there are interface ICs that use 16bit word length? There are all the older ones from Sony, Yamaha, NPC etc, most of them available cheaply from China today.
I have CS4316, DIR9001 and WM8805 receiver chips, I haven't looked much at the older ones, but I can check some datasheets for ones that will accept a 16-bit word length.
I have CS4316, DIR9001 and WM8805 receiver chips, I haven't looked much at the older ones, but I can check some datasheets for ones that will accept a 16-bit word length.
I know you want learn something new, that is why the breadboard is handy.
You can easily work with the logic
(avoid cheap breadboards from ebay - poor contact will cause a headache).
8-bit computer update - YouTube
You can easily work with the logic
(avoid cheap breadboards from ebay - poor contact will cause a headache).8-bit computer update - YouTube
WM8805 does support a 16-bit word length, but encapsulated inside the I2S frame which has 64-bit length (plenty of 0 bits). You will need the logic for the AD768. I recommend you test it on a breadboard first
Yes offcoure but I think that word total frame length are 32bit. LE or WCLK is 32bit. Each bit is one SCK...
4 x 8bit shift register needed. Last 2 not used. Left justified format, with MSB inverted.
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IF I2S format used one simple circuit has to be added to delay LE/WCK line for one BCK and make Left justified format from I2S format.
Inverter from BCK to FlipFlop clock pin, from -Q output is new delayed WCLK, set and reset pins to +.
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Maybe is better to make this with 164 shift registers? All ouputs are at same side of chip i think?
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According to the datasheet the fs (file sample = LE = WCLK = LRCLK) is 64bit length. BCK for this fs is generated from MCLK and it is divided by 2 or by 4 resulting to 64 ... am I wrong?
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If it is 64 bit WCLK length, that is for L/R chanels, then the one chanel is 32 bit. So for 16 bits first 16 bits are word other are 0, and for 24 bit the same first 24 are data word rest up to 32 bits are zeroes.
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For DIR9001 Yo have 2 options:
1. 24bit Left justified
2. I2S (also left jusified with WCLK 1xBCK prior to the MSB) You need simple circuit to make Left Just. format
Usefull link for the DIR receiber is
DIR9001 SPDIF decoder,
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For WM8804 and WM8805 You have 3 options to choose. Again with I2S choosen You will ned simple correction circuit.
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I will post the circuits
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For DIR9001 Yo have 2 options:
1. 24bit Left justified
2. I2S (also left jusified with WCLK 1xBCK prior to the MSB) You need simple circuit to make Left Just. format
Usefull link for the DIR receiber is
DIR9001 SPDIF decoder,
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For WM8804 and WM8805 You have 3 options to choose. Again with I2S choosen You will ned simple correction circuit.
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I will post the circuits
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The specs that worry me are that monotonicity is only guaranteed for 13 bits, and the distortion levels are 12 bit equivalent. Sigma-delta DACs typically do a lot better. There must also be some compromise for high speed operation, Pushing 16 bits to 30MSPS requires a different set of trade offs compared to 48kSPS.
However the good news is you can do heavy over-sampling and noise shaping with such a chip, improving its ENOB, but how much improvement depends on
the nature of the imperfections of the DAC response - dither/noise shaping should spread the effect of DNL, but the non-linear INL response isn't going to go away so easily.
They do better yes but entirely by software (DEM). What's the basic performance of an ESS type of switched resistor DAC when you exclude all the DSP? It has to be considerably worse than the specs for AD768 as getting to those specs is what makes an AD768 cost 56euro on Mouser.
Now I'll grant that a switched resistor DAC has the advantage that there are many ways to produce a single output code so the DSP has more degrees of freedom to randomize the errors. That may well make all the difference, I've not dug deeply enough into DAC technology. If that does turn out to be the case we can add more DAC chips given that they're jolly cheap. Power consumption might be an issue though as they do run a bit warm.
I think that AD768 is segmented dac architecture. First few MSBits are encoded to Thermometer code. That is (2**N)-1 bits IF the 4 MSB used that will be 15 bits from starting 4 bits. If the 5 MSBs are used for the first segment, that will be 31 bit. That thermometer bits are going to conversion with only R component network. Other rest LSB bits are classic R2R net...
(Number of MSBs-to-thermometer probably stated in the datasheet? Or could be maybe traced from die photo? But it is 3 or 4 not more)
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So the "precision" is high.
And there are 2 modules inside for ballanced opperation.
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I think that dac is good. Friend tested some parallel data input dac long time ago and it was very food sound.
(Number of MSBs-to-thermometer probably stated in the datasheet? Or could be maybe traced from die photo? But it is 3 or 4 not more)
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So the "precision" is high.
And there are 2 modules inside for ballanced opperation.
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I think that dac is good. Friend tested some parallel data input dac long time ago and it was very food sound.
Because of few proposed sch-s for thermometer encoder only one "working"
in sim-spice that i "tested" and will try to made some dac with that segment...
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Some close to common-sense number of MSBs to send to Thermoter is limited to first 4 that is for 15. Advantages may be, single R value network (like fir DSD used). I think that still these Rs should be from small tolerances. But I will report and will start from worst case 1% test...
Next this midlle-complicated thermometer circuit adding some delay probably could be corrected to all other net lines?
in sim-spice that i "tested" and will try to made some dac with that segment...
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Some close to common-sense number of MSBs to send to Thermoter is limited to first 4 that is for 15. Advantages may be, single R value network (like fir DSD used). I think that still these Rs should be from small tolerances. But I will report and will start from worst case 1% test...
Next this midlle-complicated thermometer circuit adding some delay probably could be corrected to all other net lines?
I've made a start putting this thing together. I have used resistor arrays in sockets so if the 220r value proves to be too high, it's a simple job to change it.
The vertical board is the power supply for the DAC chip, I wanted to place it as close as possible, hence the orientation. Some ofthe decoupling caps could fit on the main PCB, the white ones are EVOX MMK 0.1uF, the yellow ones are 1uF, not sure if they are polyester, polycarbonate or polypropylene, just using what I have. The silver cylinders are 100uF tantalums.
The 595 modules had to be mounted upside down to have the pins in the right order to match up with the input pins of the DAC. I haven't soldered those modules in place, just pushed them into the holes on the PCB to check if they will fit. There is plenty of room to add more logic, I won't solder any of the logic in place until we have finalised the designed, I just wanted to put the DAC chip and it's power supply arrangements together to get an idea of how things will fit together.
The vertical board is the power supply for the DAC chip, I wanted to place it as close as possible, hence the orientation. Some ofthe decoupling caps could fit on the main PCB, the white ones are EVOX MMK 0.1uF, the yellow ones are 1uF, not sure if they are polyester, polycarbonate or polypropylene, just using what I have. The silver cylinders are 100uF tantalums.
The 595 modules had to be mounted upside down to have the pins in the right order to match up with the input pins of the DAC. I haven't soldered those modules in place, just pushed them into the holes on the PCB to check if they will fit. There is plenty of room to add more logic, I won't solder any of the logic in place until we have finalised the designed, I just wanted to put the DAC chip and it's power supply arrangements together to get an idea of how things will fit together.
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Hi
2 options for serial to parallel data.
One with 164 familly (tested and working with I2S input Diskrete DAC serial interface)
Second, with 595 familly logic, (I tested with DSD format, but it will work for this purpose). Enable is negative and could be use as MUTE when connected to +V, or HI
2 options for serial to parallel data.
One with 164 familly (tested and working with I2S input Diskrete DAC serial interface)
Second, with 595 familly logic, (I tested with DSD format, but it will work for this purpose). Enable is negative and could be use as MUTE when connected to +V, or HI