Your ****-up could have been avoided if you actually read the ADR02 data sheet, which is titled "Ultracompact Precision 5.0V Voltage Reference". A Voltage Reference is not the same as a Voltage Regulator. What's more, if you actually read the AD768 datasheet you would know the AD768 contains a 2.5V voltage reference, which means a precision power supply is not necessary.
After some thought and reading of various app notes and articles, it seems that the way to use the ADR02 to create a higher output regulated supply is to build a circuit around it using an op amp and a MOSFET. I found several circuit examples, all very similar, this one was in the ADR02 datasheet, an identical circuit was found in an article from Analog Devices that differed only in which op amp was used. This circuit will deliver 50mA, if I interpret the text correctly, by changing the MOSFET you can get more current.
But is 50mA enough for an AD768? Not according to the datasheet :
So the problem is that the ADR02 on it's own only delivers 10mA, but the AD758 requires between 3 and 7 times that amount of current on it's positive and negatives lines respectively. The answer is to build a circuit around the ADR02 using an opamp and MOSFET and you must select a MOSFET that will give sufficient output current.
Now I have to ask, is it worth the effort to continue along this path of using the ADR02 and additional components to build a high precision low noise supply for the DAC chips or would it be more sensible to just use a conventional voltage regulator such as a 7805 and 7905 to create the 5v dual rail supply the AD768 needs? Certainly the 7805/7905 option is much simpler to implement.
But is 50mA enough for an AD768? Not according to the datasheet :
So the problem is that the ADR02 on it's own only delivers 10mA, but the AD758 requires between 3 and 7 times that amount of current on it's positive and negatives lines respectively. The answer is to build a circuit around the ADR02 using an opamp and MOSFET and you must select a MOSFET that will give sufficient output current.
Now I have to ask, is it worth the effort to continue along this path of using the ADR02 and additional components to build a high precision low noise supply for the DAC chips or would it be more sensible to just use a conventional voltage regulator such as a 7805 and 7905 to create the 5v dual rail supply the AD768 needs? Certainly the 7805/7905 option is much simpler to implement.
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I suggest you to do it as simple as possible for basic functionality (so yeah, 7805/7905). As your device catch a breath, additional improvements can be added later - one after another and the change will be easier to "notice". This way you can tell more clearly, if the complicated change made sense or if it is better to stay simple 
Cheers miro, that sounds eminently sensible. Contrary to what trolls might say, I actually spent too much time reading datasheets, so ended up reading all the Analog Devices marketing text about how this chip and that chip was eminently suitable for high precision ADC/DAC systems yada yada, hence the ADR02, but I committed the rookie mistake of not checking all the technical data and thereby noticing it was capable of only 10mA.
I lost sight of the wood for the trees, so as you suggest, simplify things. I'll root in my boxes and find some 7805s and 7905s and sort out the power supplies, then return to laying out the logic, I've spent a lot of time yesterday and today looking at Zoran's schematics and finally have figured out how it works and how to apply it to my application, it took a while for the penny to drop and figure out what Zoran was trying to teach me, but it was a very valuable lesson, so I am most grateful for the help.
I lost sight of the wood for the trees, so as you suggest, simplify things. I'll root in my boxes and find some 7805s and 7905s and sort out the power supplies, then return to laying out the logic, I've spent a lot of time yesterday and today looking at Zoran's schematics and finally have figured out how it works and how to apply it to my application, it took a while for the penny to drop and figure out what Zoran was trying to teach me, but it was a very valuable lesson, so I am most grateful for the help.
I have redrawn the schematic using Zoran's guidance, I've also redone the power arrangements to use the good old 7805/7905:
However, it occurred to me that it might be more sensible to add a second AD768 (I have 5 of them) so that the device can handle not just 16-bit data, but can process 32 bits which will allow it to handle not just CDs but more modern digital formats too.
The difference in complexity in adding a second AD768 isn't very great, I duplicated the +/-5V supply, but I could simplify things by supplying both AD768s from a single dual rail supply.
The way this is setup, for left justified data input, would it support DSD as well as PCM formats? Maybe I should build this device to support DSD as well as PCM, it seems sensible to build this device to be capable of handling more than just 16-bit 44.1kHz input.
However, it occurred to me that it might be more sensible to add a second AD768 (I have 5 of them) so that the device can handle not just 16-bit data, but can process 32 bits which will allow it to handle not just CDs but more modern digital formats too.
The difference in complexity in adding a second AD768 isn't very great, I duplicated the +/-5V supply, but I could simplify things by supplying both AD768s from a single dual rail supply.
The way this is setup, for left justified data input, would it support DSD as well as PCM formats? Maybe I should build this device to support DSD as well as PCM, it seems sensible to build this device to be capable of handling more than just 16-bit 44.1kHz input.
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No, that wouldn't be more sensible. Because to make a useful 32 bit DAC, the precision of the second DAC chip would need to be 65,536X that of the first one. And it would need to maintain that precision with a reference 65k times smaller than the first IC. Using 5 DACs in parallel though could give you a couple more bits (using software) so the ENOB might approach 16 in practice.
You can support DSD with just the one chip given that it has no difficulty running at 2.8MHz (less than 10% of its rated speed). You can even incorporate a volume control.
I suggest you to do it as simple as possible for basic functionality (so yeah, 7805/7905). As your device catch a breath, additional improvements can be added later - one after another and the change will be easier to "notice". This way you can tell more clearly, if the complicated change made sense or if it is better to stay simple
I agrre with Miros note.
Yes start with simple and compact power solutions. (These ICs are made for this purposes.) Latter after test done, You can make more apropriate and better power supply units. With a chance to test differences with power supplu too? Like You already sketch on the schematic...
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I can suggest to put DAC chip on separate plate and serial-to-parallel interface to another test-pcb. You can connect these 2 mdules via some common type of connector.
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About DSD.
I am not sure but MAYBE You can acheive DSD conversion for only 4 bits. Because/IF the first segment of the DAC is 4 bits. In this segment is not present R2R net but only serial R to output?
You can try it but with another type of interface:
4 flip-flop IC is needed. Maybe other inputs (from MSB-5 to LSB) should be on LO or HI state?
I will post sch latter.
I am not sure but MAYBE You can acheive DSD conversion for only 4 bits. Because/IF the first segment of the DAC is 4 bits. In this segment is not present R2R net but only serial R to output?
You can try it but with another type of interface:
4 flip-flop IC is needed. Maybe other inputs (from MSB-5 to LSB) should be on LO or HI state?
I will post sch latter.
Excellent, thanks for the advice guys, I am taking careful note of all of it.
I also had the idea of putting the serial to parallel logic on a separate board when I was drawing out the schematic and trying to visualise how I would physically put it together. I have some suitable connectors and wires I could use. I shall draw up another revision of the schematic to take account of the separate boards, I find it helps me to be able to visualise and figure out potential issues if I draw it before building it.
I'll worry about DSD later, as you say, keep things simple and let's get it working, then worry about enhancements and changes later.
I also had the idea of putting the serial to parallel logic on a separate board when I was drawing out the schematic and trying to visualise how I would physically put it together. I have some suitable connectors and wires I could use. I shall draw up another revision of the schematic to take account of the separate boards, I find it helps me to be able to visualise and figure out potential issues if I draw it before building it.
I'll worry about DSD later, as you say, keep things simple and let's get it working, then worry about enhancements and changes later.
I am thinking now where is the LE/WCLK signal? It is not present as input pin on the DAC.
So the IC will "oerate" all of the time even the other channel is "ON"?
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I will try to add WCK/LE signal at parallel interface at -OE pin.
simple inverter will d the job for L channel use signal "0" (enable 595 registers), in the same time after inverter will be "1" and disblaes R channel.
And opposite.
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(To disable L+R interfaces we can add simple additional gate which will output "1" when needed?)
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I will try to draw this sch but it is pretty clear?
So the IC will "oerate" all of the time even the other channel is "ON"?
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I will try to add WCK/LE signal at parallel interface at -OE pin.
simple inverter will d the job for L channel use signal "0" (enable 595 registers), in the same time after inverter will be "1" and disblaes R channel.
And opposite.
.
(To disable L+R interfaces we can add simple additional gate which will output "1" when needed?)
.
I will try to draw this sch but it is pretty clear?
It seems logical. (I just took fast look at the datas...)
When parallel data already loaded just need signal for "send" to convertion.
In that case serial to parallel interface should be all time enabled -EN to GND
and LE line should go to DAC pin 16.
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If conversion going vith rising clock of LE that happening when LE changing state from L to tight datas, so tmaybe the outputs will be L-R swithched? Or invert the LE line.
And maybe LE line should be rearanged for one and more BCK after every 32bit word "window" or after L+R 64bit "window"?
Anyway it is not is big deal...
When parallel data already loaded just need signal for "send" to convertion.
In that case serial to parallel interface should be all time enabled -EN to GND
and LE line should go to DAC pin 16.
.
If conversion going vith rising clock of LE that happening when LE changing state from L to tight datas, so tmaybe the outputs will be L-R swithched? Or invert the LE line.
And maybe LE line should be rearanged for one and more BCK after every 32bit word "window" or after L+R 64bit "window"?
Anyway it is not is big deal...
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This is LE lines for AD768. For Left Justified format. (Based on the Philips I2S bus serial-parallel).
Theare are 3 lines WSP_LJ is 1 BCK after every WCLK changing the state.
Lenable is one BCK after WCLK=0 every time
Renable is one BCK after WCLK=1 every time
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Inclouding unchanged LE line, or optionaly with these additional 3 sygnals DAC can be set to conversion.
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Theare are 3 lines WSP_LJ is 1 BCK after every WCLK changing the state.
Lenable is one BCK after WCLK=0 every time
Renable is one BCK after WCLK=1 every time
.
Inclouding unchanged LE line, or optionaly with these additional 3 sygnals DAC can be set to conversion.
.
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How about 18bit DAC729?
I am glad to see this thread as I probably can modify the circuit to make DAC729.
DAC729 is an instrument-grade DAC of PCM64, which is 18 bit, 2 more bit than AD768 mentioned here and parallel-input too.
I plan to build a dual mono DAC729 with Ian's FIFO I2S input, so a serial to parallel conversion is a must.
So, as schematic attached, can I just connect the extra 2 bit to the third 74HC374 and ignore the rest?
And, overall, is this schematic for I2S to DAC729 correct?
There is barely no info about PCM64 and DAC729 for direct NOS I2S, so seeing AD768 R2R being disccused is inspiring.
For sure I can use it as a 16bit DAC so that problem could be easier, but I just want to figure out how 18bit work.
Thanks for help, any comments are welcomed.
I am glad to see this thread as I probably can modify the circuit to make DAC729.
DAC729 is an instrument-grade DAC of PCM64, which is 18 bit, 2 more bit than AD768 mentioned here and parallel-input too.
I plan to build a dual mono DAC729 with Ian's FIFO I2S input, so a serial to parallel conversion is a must.
So, as schematic attached, can I just connect the extra 2 bit to the third 74HC374 and ignore the rest?
And, overall, is this schematic for I2S to DAC729 correct?
There is barely no info about PCM64 and DAC729 for direct NOS I2S, so seeing AD768 R2R being disccused is inspiring.
For sure I can use it as a 16bit DAC so that problem could be easier, but I just want to figure out how 18bit work.
Thanks for help, any comments are welcomed.
