G.Kleinschmidt said:
Glen,
I think I lost track of what you were doing. Are these slewing numbers in regard to driving no-load, 8 ohm load, or 1 ohm load?
The reason I ask is that the rate of change of current is the parameter I'm thinking of. If you are having trouble beyond 80V/us into a light load, then I guess the problem has more to do with driving the device capacitances.
If you are trying to drive 200V/us into, say, a 1 ohm load, even with BJT ft's of 20 MHz, that is a very large current rate of change that will translate into a very large required base-suckout current.
There is a simple formula I posted somewhere here that equates the required base discharge current with the ft of the BJT and the rate of change of current. I think it might have gone something like this:
Ib = (dI/dt)/(2*pi*ft)
I'm just doing this off the top of my head, so please forgive me if I've got it wrong.
If you plug in 200 V/us into 1 ohm you get 200 A/us. If you plug in ft = 20 MHz, you get Ib = 1.6 Amps.
Cheers,
Bob
john curl said:Stick with what you know, fellow engineers.
Thanks John.
I’m going to stick with triple EF bipolar drivers here (parallel MJL150(28/29) in the middle).
BTW, when you have finished building a single ended 800W into 1 ohm, 120A peak design with bias for 200W into 4 ohms in class A, regulated rails for the output stage, a front end with easilly under 0.001% THD-20 at full amplitude that slews ~200V/uS let me know.
Here is a preliminary schematic of the driver circuit for the output stage consisting of 20 parallel pairs of MJL1302/MJL3281 biased at 5A Iq.
The 4 parallel pairs are 30MHz fT MJE15032 / MJE15033. Total bias for these four pairs is 560mA
The single pair driving those are also MJE15032 / MJE15033.
The Vbe multiplier transistors are BD139 / BD140.
The current source and VAS buffering transistors are ultra low Cob (a few pF), 150MHz fT types KSC3503 / KSA1381. This extra stage of buffering is added as it is essential to keep the capacitive load on the VAS as low as possible for the highest possible slewrate.
Not included in the schematic is the VAS voltage clamp to limit the minumum Vce of the output transistors to ~4V and the over current (120A) protection.
The 4 parallel pairs are 30MHz fT MJE15032 / MJE15033. Total bias for these four pairs is 560mA
The single pair driving those are also MJE15032 / MJE15033.
The Vbe multiplier transistors are BD139 / BD140.
The current source and VAS buffering transistors are ultra low Cob (a few pF), 150MHz fT types KSC3503 / KSA1381. This extra stage of buffering is added as it is essential to keep the capacitive load on the VAS as low as possible for the highest possible slewrate.
Not included in the schematic is the VAS voltage clamp to limit the minumum Vce of the output transistors to ~4V and the over current (120A) protection.
Attachments
VAS buffer
Hi Glen,
You really like large numbers, don't you?
Never mind. So you want to lower the capacitive load on the VAS. Why not use a diamond buffer and tie the collectors of the 1st transistor pair to a signal that follows the VAS output voltage. Then the capacitive load is even lower and you don't need ultra small Cob trannies.
In practice, this means:
- interchange Q11 and Q12
- tie their collectors to +DRV and -DRV respectively.
- tie the current sources to the emitters of Q11 and Q12 respectively
- redesign the bias generator (of course).
Let me know what you think about it, please.
Cheers, Edmond.
BTW, my latest design has such VAS buffer.
G.Kleinschmidt said:
Hi Glen,
You really like large numbers, don't you?
Never mind. So you want to lower the capacitive load on the VAS. Why not use a diamond buffer and tie the collectors of the 1st transistor pair to a signal that follows the VAS output voltage. Then the capacitive load is even lower and you don't need ultra small Cob trannies.
In practice, this means:
- interchange Q11 and Q12
- tie their collectors to +DRV and -DRV respectively.
- tie the current sources to the emitters of Q11 and Q12 respectively
- redesign the bias generator (of course).
Let me know what you think about it, please.
Cheers, Edmond.
BTW, my latest design has such VAS buffer.
Har, har, har!john curl said:Kleinschmidt, I was doing over 500V/us and the equivalent of more than 1000W into 1 ohm back in 1981, with a regulated power supply and 3 airblown heatsinks. Please don't think you are outdoing me, yet!
LOL!
I want single ended and well under a whopping 0.15% THD-20 please.
BTW, what is the slew rate of the JC-1 again?
Re: VAS buffer
Hi Edmond
That would work also and I could then get away with higher Cob trannies for the VAS buffer, but I need the low Cob devices for the VAS cascodes anyway, so it isn’t much trouble to use a few more in the circuit. These low Cob parts also have high fT, which is desirable also.
With just the simple complementary EF buffer, the loading on the VAS is pretty much neglible and the slew rate isn’t significantly effected.
I also have layout / manufacturing considerations to consider in this design, due to it’s power rating and size. As you can see in my schematic above, the VAS buffer is in a darker background. This is because I want to have it on the shielded input/VAS circuit board, which is separate from the driver and OPS biasing board.
Cheers,
Glen
Edmond Stuart said:
Hi Edmond
That would work also and I could then get away with higher Cob trannies for the VAS buffer, but I need the low Cob devices for the VAS cascodes anyway, so it isn’t much trouble to use a few more in the circuit. These low Cob parts also have high fT, which is desirable also.
With just the simple complementary EF buffer, the loading on the VAS is pretty much neglible and the slew rate isn’t significantly effected.
I also have layout / manufacturing considerations to consider in this design, due to it’s power rating and size. As you can see in my schematic above, the VAS buffer is in a darker background. This is because I want to have it on the shielded input/VAS circuit board, which is separate from the driver and OPS biasing board.
Cheers,
Glen
