See attached image. I did question about this. Lets consider negative going signal, Q1 is kept on in Class A because Q2 pull Q4 low, in turn pull Q3 low as shown in the path in RED. Q1 really does not have to be responsible to pull the base of Q3 low. So even when I use 68ohm for R1(21mA), Q1 is going to stay class A. Am I correct. This means I can lower the current down to even 10mA and Q1 will stay on all the time.
Seems to me if you actually run 100W into 4ohm load, the output transistors has to drive 20Vpeak and current is 5A peak. For beta=50, the base drive is 100mA. The driver heat up because it needs to provide that 100mA.
Are you saying you intentionally run lower idle current in the drivers to keep the Vbe a little low, then when large signal comes in, the Drivers has to drive large current and the dynamic Vbe increase and DYNAMICALLY biased the big power transistors hotter during the large signal incursion? That is smart!!!
Thanks for replying. This make me think more. Please comment on my rationing here to see whether I am correct or not.
I put such a small heat sink because I mistakenly having too little space between the two drivers, I eventually has to re-layout the board to fit a bigger heat sink.
I have to watch the woman soccer final now!!
Thanks
Attachments
Who would play a 200W square wave through their speakers?
The predrivers see very little of this "spike" , they are not class B
like the outputs , less Cob ... as well.
The outputs are the only semi's that are actually switching.
Total "overkill" !
OS
I guess we don`t understand each other very well, I`ll send the simulation pictures and explaining tomorrow
Yes, I'm just lazy.
Aluminum is harder, I don't have enough separation between Q7 and Q8 to squeeze a thick aluminum plate as they are like 1/8" thick. Copper plate is more expensive to buy and usually comes in long strips in Home depot.
I did not think of more power dissipation than idle when the signal level is high. Now I might have to think again. If I just have a little more separation between Q7 and Q8, I could have found a scrap heatsink that can fit in between.
My board is layout too tight to save money. I should have relax it a little. The next go around, I definitely increase the width at least 1/4" and make it 1" longer to space out the power transistor a little for better heat dissipation.
After reading Ostripper's post a few times, I am curious in the dynamic voltage of the drivers and the big output transistors at different points.
Attached is the drawing showing the drivers Q1 and Q2 driving the output transistor Q3 and Q4 respectively, through 2.2ohm base stop resistors R4 and R5. Assume the emitter degen resistor R2 and R3 are 0.22ohm. Assume idle current is small. At idle, current through Q1 and Q2 is set by 1.4V/68=20mA. This is shown in black in the drawing. Assuming all Vbe are 0.7V.
Now let's look at the situation of large signal input where the -ve Vpeak = -50V at the output driving a 4ohm load. The peak current is 12.5A as shown in RED. Let us trace the voltage from the output CLOCKWISE all the way to the emitter of Q1.
1) -50V at output, Q4 sinking 12.5A.
2) R3 has 12.5A, so it drops 12.5A X 0.22ohm = 2.75V. Therefore the emitter of Q4 is -52.75V.
3) Assuming Vbe=0.7V. The base of Q4= -52.75-0.7=-53.45V.
4) Assume beta of Q4=50, Q4 sinking 12.5A implies the base current is 12.5/50=0.25A.
5) voltage drop across the 2.2ohm R5 base stop resistor is 2.2 X 0.25= 0.55V. Therefore the emitter of Q2 is -54V.
6) Assume again Vbe of Q2 is 0.7V, therefore the base of Q2 is at -54.7V.
7) The bias spreader is 2.8V, therefore the base of Q1=--54.7+2.8V=-51.9V.
8) The emitter of Q1 is -51.9-0.7V=-52.6V.
9) The voltage dropped across the resistor R1 between the emitters of Q1 and Q2 is -52.6+54=1.4V. The current through R1 does not change!!!
Of cause the current increase in Q2 and Q4 is going to increase the Vbe of these two transistor. Let's just say the total Vbe increase is 200mV ( this is a lot as it's a logarithmic function). The voltage drop across R1 is 1.4-0.2=1.2V. Current through Q1 and Q2 is 1.2/68=17.6mA. It's nowhere close to turning off.
Please take a look at my work. If this is correct, people NEVER have to worry about the driver transistor being turned off under signal as the current increase for Q1 when Q2 is driving low hard. You can lower the idle current to less than 20mA without even worry about any drivers being turned off. They will ALWAYS stay in Class A.
Attached is the drawing showing the drivers Q1 and Q2 driving the output transistor Q3 and Q4 respectively, through 2.2ohm base stop resistors R4 and R5. Assume the emitter degen resistor R2 and R3 are 0.22ohm. Assume idle current is small. At idle, current through Q1 and Q2 is set by 1.4V/68=20mA. This is shown in black in the drawing. Assuming all Vbe are 0.7V.
Now let's look at the situation of large signal input where the -ve Vpeak = -50V at the output driving a 4ohm load. The peak current is 12.5A as shown in RED. Let us trace the voltage from the output CLOCKWISE all the way to the emitter of Q1.
1) -50V at output, Q4 sinking 12.5A.
2) R3 has 12.5A, so it drops 12.5A X 0.22ohm = 2.75V. Therefore the emitter of Q4 is -52.75V.
3) Assuming Vbe=0.7V. The base of Q4= -52.75-0.7=-53.45V.
4) Assume beta of Q4=50, Q4 sinking 12.5A implies the base current is 12.5/50=0.25A.
5) voltage drop across the 2.2ohm R5 base stop resistor is 2.2 X 0.25= 0.55V. Therefore the emitter of Q2 is -54V.
6) Assume again Vbe of Q2 is 0.7V, therefore the base of Q2 is at -54.7V.
7) The bias spreader is 2.8V, therefore the base of Q1=--54.7+2.8V=-51.9V.
8) The emitter of Q1 is -51.9-0.7V=-52.6V.
9) The voltage dropped across the resistor R1 between the emitters of Q1 and Q2 is -52.6+54=1.4V. The current through R1 does not change!!!
Of cause the current increase in Q2 and Q4 is going to increase the Vbe of these two transistor. Let's just say the total Vbe increase is 200mV ( this is a lot as it's a logarithmic function). The voltage drop across R1 is 1.4-0.2=1.2V. Current through Q1 and Q2 is 1.2/68=17.6mA. It's nowhere close to turning off.
Please take a look at my work. If this is correct, people NEVER have to worry about the driver transistor being turned off under signal as the current increase for Q1 when Q2 is driving low hard. You can lower the idle current to less than 20mA without even worry about any drivers being turned off. They will ALWAYS stay in Class A.
Attachments
It does. The circuit is sensitive to PSU ripple and sag. Can be solved replacing R3/R31 with current sources.
The circuit can do more than just prevent saturation of the CCS transistor. Proper dimensioned it can shape the clipping behaviour of the amplifier back-end. But it has some drawbacks like the capacitance of the reverse biased diodes.
I since did more thinking. This conclusion is not exactly correct. The current really depends on the values of R3 and R5, the emitter resistor and the base stop resistor. The higher the value they are, the more voltage they drop. Mostly the emitter resistor R3 dominates the effect as during high current like 12.5A, the drop across 0.22ohm is 2.75V.
This observation can draw more conclusion. If you have 0.22ohm, change of current of the drivers are minimal. Using 0.15, less voltage drop across R3, the current actually increase during high current.
The more important is if you use 0.47ohm for R3. It will drop 5.87V, over 3V more than if the resistor is 0.22ohm. If you calculate the loop again, Q1 is going to be turned off.
Please verify, if my rationing is correct, you better not use emitter degeneration resistor over 0.22ohm!!!!
Or am I missing something?
Alan,
you are lost. You just don't understand.
If you have a single pair output stage then you can analyse your current flows and voltage drops using actual component parameters.
When you move to multiple output pairs you MUST change your analysis to reflect the way the currents are shared between the paralleled devices.
An easy way is to calculate the Re value to be inserted into your analysis that equals the paralleled equivalent to 5 off 0r22. i.e. 0r44 and when your chosen 12.5Apk flows the voltage drop becomes 0.55V, not 2.75V
In post5645 you state all Vbe = 0.7Vbe.
That is reasonable for Q2 & Q4 that are passing your peak current.
But Q1 and Q3 are passing near zero current. Vbe for these two will be <<0.7Vbe.
Maybe even lower than 0.5Vbe
Your +-1.4Vbias voltage does not change. It should still be the quiescent value set up to turn the Vre on to their preset value. expect four Vbe of around 570mVbe to 620mVbe plus two Vre of around 20mVre
that totals ~1.22Vbias. That should not change The capacitor across the Vbe multiplier tries to hold this constant.
The Vbe multiplier itself is a shunt voltage regulator that tries to hold this value.
You can't willy nilly turn up Vbias to suit your assumption that all the transistors stay in ClassA !
You need to understand the operation to be able to design.
I find the DC side easy, but have never really learned the AC side.
You can't even do the DC part.
Your current sources are an example.
Your heatsink analysis is yet another.
you are lost. You just don't understand.
If you have a single pair output stage then you can analyse your current flows and voltage drops using actual component parameters.
When you move to multiple output pairs you MUST change your analysis to reflect the way the currents are shared between the paralleled devices.
An easy way is to calculate the Re value to be inserted into your analysis that equals the paralleled equivalent to 5 off 0r22. i.e. 0r44 and when your chosen 12.5Apk flows the voltage drop becomes 0.55V, not 2.75V
In post5645 you state all Vbe = 0.7Vbe.
That is reasonable for Q2 & Q4 that are passing your peak current.
But Q1 and Q3 are passing near zero current. Vbe for these two will be <<0.7Vbe.
Maybe even lower than 0.5Vbe
Your +-1.4Vbias voltage does not change. It should still be the quiescent value set up to turn the Vre on to their preset value. expect four Vbe of around 570mVbe to 620mVbe plus two Vre of around 20mVre
that totals ~1.22Vbias. That should not change The capacitor across the Vbe multiplier tries to hold this constant.
The Vbe multiplier itself is a shunt voltage regulator that tries to hold this value.
You can't willy nilly turn up Vbias to suit your assumption that all the transistors stay in ClassA !
You need to understand the operation to be able to design.
I find the DC side easy, but have never really learned the AC side.
You can't even do the DC part.
Your current sources are an example.
Your heatsink analysis is yet another.
Ask the Moderators to extract all your posts and replies (you will need to list them) and insert into a new Thread. A few may require to be copied if they are relevant to Bob Cordell's "book" Thread.
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+1... hallelujah! It's about time that the Mods move all the OT posts from this once fine thread - including this one...
Surely a "30-year EE" doesn't need that much help to design an amplifier - is the electronic theory somehow different for audio?!
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If someone would be willing to go through and provide a list of the posts to be moved, we can do it. Use the "report" button on any of them so that whatever mod is online will have the list.
Everything starting with #5533. If there is anything belonging to Mr. Cordell's thread, it would be much easier to be eventually brought back. Delete this.
New thread
I want Alan and everyone else that has participated here that I have not had any problem at all with Alan's many questions. Alan is a smart guy and has raised some very good questions, especially for an audio power amplifier newbie. The back and forth on these questions is one of the important ways we all learn from each other. In fact it has greatly contributed to my own understanding and has played a big role in formulating my book. None of us, including those more experienced, should ever hesitate to ask what we might think of as a dumb question, especially for fear of looking ignorant. We should always feel free to lean on the other smart and generous people on this forum.
For me, personally, I try never to avoid asking what might be a dumb question, because we never know where the subsequent discussion (or even arguments) may lead.
I worked very hard to make my book helpful to the less experienced while going deeply into more advanced subjects. This was quite a challenge. When people like Alan raise some of these types of questions, it is helpful to me to make my second edition better. It is amazing how sometimes one sentence or one paragraph or one more figure can answer such questions. Often, authors don't know what they don't know, or don't know what many in their audience might not know.
If Alan and others can ask questions that are not clearly answered in my book (after reading the relevent section(s) throughly) that can help me a lot.
Cheers,
Bob
I want Alan and everyone else that has participated here that I have not had any problem at all with Alan's many questions. Alan is a smart guy and has raised some very good questions, especially for an audio power amplifier newbie. The back and forth on these questions is one of the important ways we all learn from each other. In fact it has greatly contributed to my own understanding and has played a big role in formulating my book. None of us, including those more experienced, should ever hesitate to ask what we might think of as a dumb question, especially for fear of looking ignorant. We should always feel free to lean on the other smart and generous people on this forum.
For me, personally, I try never to avoid asking what might be a dumb question, because we never know where the subsequent discussion (or even arguments) may lead.
I worked very hard to make my book helpful to the less experienced while going deeply into more advanced subjects. This was quite a challenge. When people like Alan raise some of these types of questions, it is helpful to me to make my second edition better. It is amazing how sometimes one sentence or one paragraph or one more figure can answer such questions. Often, authors don't know what they don't know, or don't know what many in their audience might not know.
If Alan and others can ask questions that are not clearly answered in my book (after reading the relevent section(s) throughly) that can help me a lot.
Cheers,
Bob
Which part do you NOT understand in my drawing that I am talking about single output pair?
This is a basic analysis of how the emitter and base stop resistor affect the bias of the drivers. You can use this to extend to 5 pairs. Vbe is not going to vary over 20mV or so, even for 5 pairs, the resistors still going to the major part of the variable here and what I said still applies. It still shows the trend that higher Re will decrease the current of the drivers under large signal.
What's wrong with my current source?
Why don't you put in your analysis then?
Hi Mr. Cordell
Thanks for your encouragement. I do feel the same way. and on top, I think there are a lot of people might not understand it correctly and they are too proud or afraid to ask in the risk of sounding stupid. The only way to know whether you really understand is to put your thoughts out. Might not feel that good when people point out it's wrong, but sure learn. So the question is whether one want people to think they know or they really know. I might get insulted and laughed at one time, but the knowledge gain last forever.
I went back to your book this morning, actually My diamond is very close to the current setup in you Fig 10.6 in page 192. That you use 50mA of current through the drivers Q3 and Q4. I think there is a typo of 50mA. It should be 60mA like in Fig.10.7. Just a note.
I think keeping the drivers and pre-driver on 100% (Class A) of the time is important. I just want to do the DC analysis to see how it looks. Seems like the value of the emitter resistor has a lot to do with this if you look at my calculation. For 5 pairs, the effect is smaller. But most schematics I saw on this site use single or two pairs max. Blindly using 0.47ohm might put the drivers over that they got turn off during large signal excursion. Can you comment on this?
Thanks
Alan
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That is very small because it's being divided by R1/(R1+R3). More importantly the current is driving into the emitter of the pre-driver Q8 which r'e = 2.6ohm. It's not going to make a difference.
Q: Is IS the correct parameter for Vbe in BJT models to step on?
Hi Bob and all,
I'm in the middle of building an amp that has a mirror loaded, symmetric complementary IPS and a push-pull VAS, or Figure 7-10-ish circuit in Bob's book (Yeah, I admit I have poor resistance to eye candy symmetry in schematics).
The input LTP, their cascodes, and the current mirrors are dual transistors for good chances of matching and thermal coupling.
The datasheet of BCM847/857 (used in input LTP and CMs) suggests the Vbe mismatch would be max +/-2mV @Ic=2mA (happens to be the LTP transistor standing current in the amp design). I took the circuit to LTspice and stepped IS in transistor models among the 8 transistors, trying to figure out the sensitivity the VAS standing current has to such a Vbe mismatch. The LTspice allows only 3 dimensions of steeping during one simulation, so I tried different combinations of group of three. the result seem to suggest a range of VAS standing current of 4.5mA to 7.8mA being worst of all combinations.
Such a VAS standing current spread seems to be tolerable, as I employed a CCS-sort of control in the Vbe multiplier that keeps the currents that pass the Vbe sensor transistor and the ThermalTrak diodes somewhat constant over a range of VAS current.
My question is, did I do the Vbe stepping the right way? Spice does not model BJT's Vbe, as Vbe seems to be a function of IS (and perhaps other variables). What I did was attempting to step different IS around its default value in the models until I have reached +/-2mV Vbe in the simulation results.
Will appreciate all comments.
Hi Bob and all,
I'm in the middle of building an amp that has a mirror loaded, symmetric complementary IPS and a push-pull VAS, or Figure 7-10-ish circuit in Bob's book (Yeah, I admit I have poor resistance to eye candy symmetry in schematics).
The input LTP, their cascodes, and the current mirrors are dual transistors for good chances of matching and thermal coupling.
The datasheet of BCM847/857 (used in input LTP and CMs) suggests the Vbe mismatch would be max +/-2mV @Ic=2mA (happens to be the LTP transistor standing current in the amp design). I took the circuit to LTspice and stepped IS in transistor models among the 8 transistors, trying to figure out the sensitivity the VAS standing current has to such a Vbe mismatch. The LTspice allows only 3 dimensions of steeping during one simulation, so I tried different combinations of group of three. the result seem to suggest a range of VAS standing current of 4.5mA to 7.8mA being worst of all combinations.
Such a VAS standing current spread seems to be tolerable, as I employed a CCS-sort of control in the Vbe multiplier that keeps the currents that pass the Vbe sensor transistor and the ThermalTrak diodes somewhat constant over a range of VAS current.
My question is, did I do the Vbe stepping the right way? Spice does not model BJT's Vbe, as Vbe seems to be a function of IS (and perhaps other variables). What I did was attempting to step different IS around its default value in the models until I have reached +/-2mV Vbe in the simulation results.
Will appreciate all comments.
Attachments
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Hi Mr. Cordell
I have been reading p196 to 197 of your book. You gave in detail about the effect of C/pi and Ib with given bias current of the output transistors and give example of base drive requirement with 20KHz 40V peak output.
In my example on DC bias change with large signal driving 4ohm load, you can see the bias current change with different values of emitter degeneration resistor. If this is the case, do you think we should put that into part of the whole equation to find the drive requirement?
Even though my analysis is DC, but I can see a 20KHz that lasted for a split second. If there is enough cycles lapse, the DC bias of the drivers will shift as I predicted and the calculation in you dynamic requirement can be affected.
This is specially important if people use one or two stages in parallel only and try to play it safe using 0.47ohm emitter degeneration. My calculation predict the top NPN driver will be turn off under DC condition.
Can you tell me whether I am totally off?
Thanks
I have been reading p196 to 197 of your book. You gave in detail about the effect of C/pi and Ib with given bias current of the output transistors and give example of base drive requirement with 20KHz 40V peak output.
In my example on DC bias change with large signal driving 4ohm load, you can see the bias current change with different values of emitter degeneration resistor. If this is the case, do you think we should put that into part of the whole equation to find the drive requirement?
Even though my analysis is DC, but I can see a 20KHz that lasted for a split second. If there is enough cycles lapse, the DC bias of the drivers will shift as I predicted and the calculation in you dynamic requirement can be affected.
This is specially important if people use one or two stages in parallel only and try to play it safe using 0.47ohm emitter degeneration. My calculation predict the top NPN driver will be turn off under DC condition.
Can you tell me whether I am totally off?
Thanks