That was my interpretation too, based on Miro’s schematic. Also curious how losing +/-12v would impact offset circuit, if at all.
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Let me check if I have enough of those op amps...😂Nice clean work Zoom!!
Try a triple stack of AD844's
TDA1541A has DC offset because output current is not centered around zero. What is your external I/V? Is it created for TDA1541A? Maybe there it contains something ...
In general you can omitt and use +12 or +? voltage from your external I/V (if there is not +12V but another value, then resistor values must be adjusted).
Or as Vunce said, you can keep only +12V supply and do not populate components for onboard I/V
Thanks everyone for the help. I’ll probably use EUVL’s folded CEN or a regular Pass Zen, so voltage could be either 15 or 30. May just go the dedicated 12+ route.TDA1541A has DC offset because output current is not centered around zero. What is your external I/V? Is it created for TDA1541A? Maybe there it contains something ...
In general you can omitt and use +12 or +? voltage from your external I/V (if there is not +12V but another value, then resistor values must be adjusted).
Or as Vunce said, you can keep only +12V supply and do not populate components for onboard I/V
You just copy design of the Aleksandr (Abbas audio).@Zoran Is not his design similiar to this?
https://www.diyaudio.com/community/...et-binary-no-cpld-no-fpga.341478/post-6579352
... but it does not have stop-clock, that is why I created new version ...
https://www.abbasaudio.com/2020/05/17/цифро-аналоговый-преобразователь-на-td-4/
this is the new refreshed site
He did long time ago tests, and interface, probably before 2014. He published the programming structure for the Altera chip
from Quartus software progremmer. PCB is on the picture as the schematics and format results...
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@Zoran I know him under nickname "Nemo" from another forum. You can recall our old conversation about that design:
https://www.diyaudio.com/community/...et-binary-no-cpld-no-fpga.341478/post-5885606
... He send me his altera files, I tried his design as glue logic from SMD components and it did not work for me (I assume timing problems). In CPLD it can work but I have not tried it.
That is why I created different design, more glue-logic friendly approach. I tested and debugged it for a long time until it started working.
Creating the working glue-logic is pretty hard, because of timing issues. Altera simulation sometimes does not match the real glue-logic.
A lot of not-working prototypes are in my altera folder
https://www.diyaudio.com/community/...et-binary-no-cpld-no-fpga.341478/post-5885606
... He send me his altera files, I tried his design as glue logic from SMD components and it did not work for me (I assume timing problems). In CPLD it can work but I have not tried it.
That is why I created different design, more glue-logic friendly approach. I tested and debugged it for a long time until it started working.
Creating the working glue-logic is pretty hard, because of timing issues. Altera simulation sometimes does not match the real glue-logic.
A lot of not-working prototypes are in my altera folder
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