DAC AD1862: Almost THT, I2S input, NOS, R-2R

[diyiggy]

so what about the JLCSounds board and its Lrck for the board ? (vs I2StoPCM) ... with NOS.

 

[miro1360]

Even soic to dip adaptators are a problem - Miro: any soic outputt planned with a separate buf stage as well ?

Vunce did a nice job with his OPA861 separate output stage. Voltage regulator on such a board is a great benefit.
We could make some universal board in the future, that will handle additional tuning
For now use universal soic adapter and solder the legs similiar to this picture and it shortens the connections.
You can always add a capacitor from the top

 

[diyiggy]

Hi Diyiggy,
Thanks for your SMD capacitor recommendations, I spent a good portion of time yesterday researching parts.
Panasonic ECHU and ECPU series and CDE FCA acrylic series capacitors along with Susumu RS series resistors are all in my next Mouser order.

Don't ask me why, maybe bias, but I find the FCA better at ears while the ECHU are the only one with 5% option of capacitance value precision... The soldering is a mess : do instant soldering with flux and a hot (400°c) solder device : if you work fast the capacitance value don't change... if you rework the solder for whatever reason like the soldering doesn't suit your taste about its gloss etc : value will move... I solder one side at time to make the other one cooling - yes I'm paranoids with those caps ... but they sounds good- Don't try the Rubycons yet...

 

[miro1360]

so what about the JLCSounds board and its Lrck for the board ? (vs I2StoPCM) ... with NOS.

I will go with any known simple I2S solution (I don't see a benefit in reclocking for NOS R-2R). You know, everyone prefers something different For what additional reclocking when almost any xmos based PCB has jitter very low. Also pcm2706/7 is sufficient for R-2R.

 

[diyiggy]

yes I planned the extra C (any idea on the value please ? 10 nF ? 1 nF ? 100 pF ?)


just the extra soldering trace of the adaptator + the stack are maybe not safe whatever the extra effort ! But I have some and tests are planed...

 

[miro1360]

something between 47nF - 100nF is considered as a good decoupling, use foil type PP

 

[diyiggy]

Thank you .
We agree it is in plus of the pcb 100 nF that are too far for a soic adaptator - we talk stacking cap from above- ?




Edit : what I know is the tda1541A seems to profit also better from a good Lrck that a good Bck from what I readed from very experienced diyers with this chip !

 

[Joseph K]

In my pcm63 dac, the stop-clock modality is applied, too.
Merit of the original designers. And the applied NPC chip.

 

[miro1360]

@diyiggy ... according to enough space, GND leg can be longer and the power leg as short as possible

@Joseph K ... this is fine, LRCK is generated from MCLK or BCK? MCLK is better.

 

[Joseph K]

Reclocked directly from the clock oscillator.
And not only LRCLK but all signals.. A delicate task, and today I don't know if it really was worth it..

 

[Joseph K]

I mean the result is good but maybe could arrive to a similar result with less complexity..

 

[miro1360]

BCK must match the data only, but the LRCK is critical for R-2R, LRCK is the slowest signal so if it is generated from a fast clock then it will be fine

 

[Joseph K]

You know that for example, in the 1704 it is not LRCLK any more, but BCLK..
But yes, in the PCM63 it should be LRCLK the trigger signal for the conversion.

Notwithstanding Guido and troops had put a serious effort in synchronizing also BCLK, DATA. They claimed it helped.. Though after I had found many 'entry points' for mods, so it could be different now.

 

[miro1360]

PCM1704 has LRCK and is called WCLK (word clock), BCK=BCLK

 

[Joseph K]

Look up the datasheet of 1704, it is stated clearly the BCLK is the trigger for conversion. (with LRCLK (WCLk) set as a condition)

 

[miro1360]

look up the page 7 in datasheet:
"Audio data is supplied to the DATA (pin 1) input. The bit
clock is used to shift data into the PCM1704 and is supplied
to BCLK (pin 2). All DAC serial input data bits are latched
into the serial input register on the rising edge of BCLK. The
serial-to-parallel data transfer to the DAC occurs on the
falling edge of WCLK. "

WCLK = LRCK
BCLK = BCK
DATA = either DR or DL

 

[Joseph K]

I like to discuss with You, seriously..
But! You have stopped one sentence too early!!

"The change in the output of the DAC
occurs at the rising edge of the 2nd BCLK after the falling edge of WCLK."

 

[Joseph K]

It is so much so, that in the Hagdac Hagermann did not even do any flip-flop reclocking, just served the MCLK into the PCM 1704 chips (as BCLK) directly..

 

[miro1360]

It "occurs", does it mean it is aligned by? If so, this is what you meant and I did not understand properly what you meant. I understood this:
>>in the 1704 it is not LRCLK any more, but BCLK..
as: LRCLK == BCLK sorry...
Now it makes sense. The output is 2 BCLK delayed and thus "aligned" by.

 

[Joseph K]

Yes, exactly - and no problem at all!

All the best, George