As for OpAmp bypass, we have to think of it of one single capacitor from +Vs to -Vs which has a tap at the center, from where we bridge to the GND plane with vias.
This way the OpAmp rails are frozen with short low inductance paths, both with repect to GND and to each other. It also makes sure class-B supply current transients don't enter the reference GND at different points, giving rise to different error voltage drops for each polarity of return current, causing distortion. Error voltage drops can still be there but the important difference is that is a copy of the signal current which is benign (a linear error), whereas different half-wave recitified differentials are not.
For the general question, I strongly support the "only one type of capacitor but lots of it"-approach, because LC-tank circuits are your worst enemy (ESL and wiring to a larger ceramic C in conjunction with a smaller C's capacitance).
Basically a solid PCB inter-plane capacitor additionally stiched together with loads of small 0603/0402 MLCC's all over the whole board plus "spot" capacitors at every Vcc and GND pin, all of the same type (a few nF at most, usually) with no exceptions unless the other caps are large enough ESR. No extra 1uF MLCC cap at the regulator output, for example.
And you have to look at the lead frame of the IC, which in the ends limits the inductance, can't go lower than that. Imagine the actual closed current path for a transient for every GND and Vcc pin and check if the outside loop is the smallest and shortest possible, lead frame path shall dominate the picture.
This way the OpAmp rails are frozen with short low inductance paths, both with repect to GND and to each other. It also makes sure class-B supply current transients don't enter the reference GND at different points, giving rise to different error voltage drops for each polarity of return current, causing distortion. Error voltage drops can still be there but the important difference is that is a copy of the signal current which is benign (a linear error), whereas different half-wave recitified differentials are not.
For the general question, I strongly support the "only one type of capacitor but lots of it"-approach, because LC-tank circuits are your worst enemy (ESL and wiring to a larger ceramic C in conjunction with a smaller C's capacitance).
Basically a solid PCB inter-plane capacitor additionally stiched together with loads of small 0603/0402 MLCC's all over the whole board plus "spot" capacitors at every Vcc and GND pin, all of the same type (a few nF at most, usually) with no exceptions unless the other caps are large enough ESR. No extra 1uF MLCC cap at the regulator output, for example.
And you have to look at the lead frame of the IC, which in the ends limits the inductance, can't go lower than that. Imagine the actual closed current path for a transient for every GND and Vcc pin and check if the outside loop is the smallest and shortest possible, lead frame path shall dominate the picture.
Funny you mention that @KSTR. One of the layouts i'm currently working with borrowed heavily from application for large CPUs and DSPs, using patches of 24 x 0.047µF 0402 per rail. Ive never seen it used in audio, more for high speed digital, but I see no reason not to apply it in audio, so figured i'd give it a try on one of the layouts (6 layer, would be a bit more difficult to get the interplane cap with less)
That what I do, typically. The 50 (or 74) Ohms double termination of the cable to the analyzer is light enough load to not additionally add damping for anti-resonance impedance peaks. And when the DAC excites that frequency you'll clearly see the peaking. Protecion of the analyzer input is critical, and it must be AC-coupled (for RF).
FWIW, quite some people have observed the sensitivity of, for example, an AK4493 to supply impedance on the VrefH and VrevH pins. The pulse rate on those is MCLK/2 (so around ~12MHz, typically). The often seen decoupling scheme of a 10uF MLCC + 100nF MLCC can easily have its antiresonance spike right there. The current flow is also correlated to the signal, the spike currents are not uniform over time, that is. This invites modulating the supply and leads to additional distortion. For that chip, things are further congested by the Vcom pin and its decoupling... no easy way to find out what works best in advance.
Full ack. DACs with 100MHz clocks are high speed digital used for analog, in the end.
6-layer is nice since L2 and L3 have really small distance and we can double up on L4/L5, and not that much more expensive than 4-layer.
@Markw4 : Thanks again for your feedbacks and the dropbox link, Mark - very helpful, indeed 
... Regarding the opamp GND layout I can visualize this - thanks for taking the time to describe it in writing!
BTW yesterday I tried a decoupling setup consisting of 27nF 0805s (unfortunately hadn't ordered some 0603s in this value) paralleled with a 47nF 1210 (960 pH) and a 220nF 1210 (all C0G) as an alternative to the ubiquitous 100 nF capacitor (1206 C0G). Overall the noise level at the VCC pins was lowered some 10-15 dBs at all sampling frequencies - very visible. Paradoxically, however, the DAC's distortion rose about 1 dB - possibly because I had an impetus to mount more vias - thus making a more efficient grounding, yet also shortening the effective distance between VDD and VCC ground.
.. so many options.
@KSTR (& InspectorGadget): Thank you (here KSTR) also for describing the thinking behind the opamp GND layout. I will let it "simmer" ...
Regarding the decoupling "challenge" I have incidentally also been considering using a couple of PCB layers as a "first" decoupling capacitor & then adding actual capacitors throughout the PCB. Some of the considerations related to this are described in Rick Hartley's youtube video:
https://printedcircuituniversity.co...d-design-of-power-distribution-and-decoupling
FYI with this particular topic addressed from appr. 47:17.
It also has made me search for PCB "boards" (laminates) with ~ 5 micron core material - something which Dupont actually makes in Kapton (polyimide) which would also allow for a likely good-sounding PCB layer capacitor. An intriguing option. I reckon it would be even more attractive if such a thin core could be found in a PTFE laminate. Haven't found it, though.
However, the rules of inductances & capacitances appear to still apply and your suggestion of a closely spaced layer (layer capacitor) combined with multiple smaller capacitors spread out across this layer still appears to create parallel/anti-resonances. Particularly if the power source has just a small amount of inductance in relation to its output. Just to illustrate this I have attached a simulation screen-dump of what I imagine such a circuit might look like with a ~ 5mil layer spacing (polyimide core; green V2P is VCC pins entering the DAC; red is VCC pins "inside" the DAC, V1p->V1n). Am I missing something here, or ... ?
Additionally, as you note, there is the consideration of the IC's internal frame pin inductances. Again referencing the attached simulation this inductance appears to shift the optimum decoupling values (the capacitance) markedly towards lower values (depending on the pin frame inductance of course) - in this simulation it would shift from 100nF plane layer capacitance to appr. 28 nF for a 24.57 MHz decoupling optimum. And there would now be a slight anti-resonance inside the IC ...
BTW ... slightly diverting here: In an earlier thread I noticed that you had bought a VNA and had begun using it for measuring various capacitance/inductance setups. Did this VNA eventually help you design such decoupling structures - or did you end up not finding it that helpful? I am asking because I am considering one of the newer nano-VNA devices (with 90 dB dynamic range) for measuring exactly decoupling impedances, however, I don't know if it will actually be helpful in practice ... maybe the spectrum analyzer is a better approach? Any chance you have some experiences you can share?
I actually tried this but forgot to terminate it correctly - will try again, thanks!
Cheers,
Jesper
... Regarding the opamp GND layout I can visualize this - thanks for taking the time to describe it in writing!BTW yesterday I tried a decoupling setup consisting of 27nF 0805s (unfortunately hadn't ordered some 0603s in this value) paralleled with a 47nF 1210 (960 pH) and a 220nF 1210 (all C0G) as an alternative to the ubiquitous 100 nF capacitor (1206 C0G). Overall the noise level at the VCC pins was lowered some 10-15 dBs at all sampling frequencies - very visible. Paradoxically, however, the DAC's distortion rose about 1 dB - possibly because I had an impetus to mount more vias - thus making a more efficient grounding, yet also shortening the effective distance between VDD and VCC ground.
.. so many options.@KSTR (& InspectorGadget): Thank you (here KSTR) also for describing the thinking behind the opamp GND layout. I will let it "simmer" ...
Regarding the decoupling "challenge" I have incidentally also been considering using a couple of PCB layers as a "first" decoupling capacitor & then adding actual capacitors throughout the PCB. Some of the considerations related to this are described in Rick Hartley's youtube video:
https://printedcircuituniversity.co...d-design-of-power-distribution-and-decoupling
FYI with this particular topic addressed from appr. 47:17.
It also has made me search for PCB "boards" (laminates) with ~ 5 micron core material - something which Dupont actually makes in Kapton (polyimide) which would also allow for a likely good-sounding PCB layer capacitor. An intriguing option. I reckon it would be even more attractive if such a thin core could be found in a PTFE laminate. Haven't found it, though.
However, the rules of inductances & capacitances appear to still apply and your suggestion of a closely spaced layer (layer capacitor) combined with multiple smaller capacitors spread out across this layer still appears to create parallel/anti-resonances. Particularly if the power source has just a small amount of inductance in relation to its output. Just to illustrate this I have attached a simulation screen-dump of what I imagine such a circuit might look like with a ~ 5mil layer spacing (polyimide core; green V2P is VCC pins entering the DAC; red is VCC pins "inside" the DAC, V1p->V1n). Am I missing something here, or ... ?
Additionally, as you note, there is the consideration of the IC's internal frame pin inductances. Again referencing the attached simulation this inductance appears to shift the optimum decoupling values (the capacitance) markedly towards lower values (depending on the pin frame inductance of course) - in this simulation it would shift from 100nF plane layer capacitance to appr. 28 nF for a 24.57 MHz decoupling optimum. And there would now be a slight anti-resonance inside the IC ...
BTW ... slightly diverting here: In an earlier thread I noticed that you had bought a VNA and had begun using it for measuring various capacitance/inductance setups. Did this VNA eventually help you design such decoupling structures - or did you end up not finding it that helpful? I am asking because I am considering one of the newer nano-VNA devices (with 90 dB dynamic range) for measuring exactly decoupling impedances, however, I don't know if it will actually be helpful in practice ... maybe the spectrum analyzer is a better approach? Any chance you have some experiences you can share?
I actually tried this but forgot to terminate it correctly - will try again, thanks!
Cheers,
Jesper
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I'm no expert when it comes to RF properties depending on stack-up and material but looking at resources like this paper it seems close spacing really is priority #1 and then total area (multiple layers). Together with closely spaced grid stiching caps it does not get any better than a certain limit. Then it is all about how good you get at placing the chip's VCC and GND vias at the best places, together with top side fills etc and spot capacitors for adjacent lead-frame paths where the return current is likely to go. Same goes for attaching the regulator(s). Goal would be to package-limited only....
I suspect your plane modelling in the sim is not fully depicting what's really happening in a plane capacitor at RF, I would think it does much better in practice.
As for the package-limited parasitic L (and R) we want to arrive at, I could imagine corner cases where some true resistance (at RF) in GND and VCC feeds to the chip pins might improve things in that it could help dampen the effect of antiresonances formed by internal capacitance to lead-frame inductor to decoupling cap tank circuit. Give them nervous potentials some wiggle room to live and relax rather than putting them into a straight jacket, so to say
. A pet theory waiting for examination with 'picky' chips like AK4493...I'm not running my W&G analyzer that much these days because it really is an old lady by now... but enough of times it was really helpful to spot supply resonance issues. I mostly used impedance-type measurement (shunt setup) with unpowered boards, measuring directly at the supply pins of a chip (often I solder the coaxials right to the decoupling cap in question, for convenience). While C values might be off (larger) for voltage-sensitive cap types I still see any signficant anti-resonance patterns clearly (up to ~150MHz with my analyzer).
I've also done spectrum measurements on live circuit supplies but kept it to a minimum no to fry or degrade the fragile analyzer input (no chance for repair for me). In A/B comparision you see effects of changes to the supply but the impedance plot is really much easier and safer to create and shows way more information. I never tried impedance measurement on noisy live digital supplies but I did that occasionally on quiet analog supplies and opamp outputs etc.
Today, I typically use the easier method of current pulse injection from a generator and look at the load-change transient, with averaging on the scope triggered by the generator... It is not that often you really need the detailed impedance vs. frequency plot after all.
@KSTR : Hi - & thanks for your elaborate feedback. Well ... I guess there may be a lot of phenomena to observe in DAC etc. decoupling which is why I hope to arrive at a reasonably predictive simulation model. It just would make things much easier than actually building the considered design each time something is to be tested ...
That may very well be - although my guess is that LTSpice would be quite precise in such relatively simple simulations. Do you have any suggestions as to what could/should be different? The included values for the plane capacitor (100 nF, first capacitor) is the resistance and inductances of a via connection plus the distance from the plane capacitor through to a top layer placed appr. 0.25 mm above the plane capacitor layers ... The other capacitor values (2nF) are taken from Kemet's capacitor simulation tool (I use a download version but also available on the internet).
Hmmm ... interesting and somehow also what I was suspecting. BTW - here assuming that one of the reasons you are not using your W&G analyzer that much is that it could be a comprehensive setup/adjustment process - have you seen these new analyzers coming up? Possibly accessible price-wise and looks like an interesting dynamic range:
https://nanorfe.com/index.html
If such equipment was available to you (assuming here that it is more straightforward to use) would you then still use the pulse injection method?
Cheers,
Jesper
That may very well be - although my guess is that LTSpice would be quite precise in such relatively simple simulations. Do you have any suggestions as to what could/should be different? The included values for the plane capacitor (100 nF, first capacitor) is the resistance and inductances of a via connection plus the distance from the plane capacitor through to a top layer placed appr. 0.25 mm above the plane capacitor layers ... The other capacitor values (2nF) are taken from Kemet's capacitor simulation tool (I use a download version but also available on the internet).
Hmmm ... interesting and somehow also what I was suspecting. BTW - here assuming that one of the reasons you are not using your W&G analyzer that much is that it could be a comprehensive setup/adjustment process - have you seen these new analyzers coming up? Possibly accessible price-wise and looks like an interesting dynamic range:
https://nanorfe.com/index.html
If such equipment was available to you (assuming here that it is more straightforward to use) would you then still use the pulse injection method?
Cheers,
Jesper
‘Im a bit late to this very interesting discussion, but looking at Jespers model, are the trace inductances at 3 nH per side right next to the pulsed load (assuming this is the DAC) not a bit high? If the cap is placed right at the supply pins and there is an assumed good quality ground plane I would have suspected lower trace inductance. The trick of paralleling capacitors to flatten the resonance points out (I guess the equivalent of reducing the Q) is well known. If you have signal components in the 100’s of MHz due to fast rise times, the required decoupling caps will be very small - a few nF at most and in very small packages - in order to reduce package inductance.
IIRC, maybe it was from Ott, putting two SMD caps right next to other in parallel, then grounding the opposite end of each cap, and driving them in parallel from the ungrounded ends causes currents to flow to ground though the caps in opposite directions. To the extent their magnetic flux partially cancels, the net inductance is reduced.
If I understand it correctly, those are meant to model the DAC's package and bond wire inductances. They are of the right order for a typical SMD package with leads and wire bonds. I suggested putting a coupling factor of about 0.5 between them if the package pins are adjacent, though.
Here's a Texas app note that covers most of the packages associated with IC's - some of the L and C figures are remarkably low, while the QFP seems exceedingly high.
https://www.ti.com/lit/an/snoa405a/snoa405a.pdf
YMMV
https://www.ti.com/lit/an/snoa405a/snoa405a.pdf
YMMV
I think X2Y are breaking the 'smaller SMD package is the better for lower inductance' heuristic using a clever novel package design. For normal SMD components, the smaller SMD packages are better for lower package inductance. You would place the 0201 or 0402 packages very close to the IC to be decoupled and then the higher value ones a bit further away and then finally the local bulk decouplers.
In case gentlevoice doesn't have enough to consider already:
https://scholar.google.com/citations?user=RvGBBxoAAAAJ&hl=en
https://www.signalintegrityjournal.com/authors/23-istvan-novak?page=2
https://scholar.google.com/citations?user=RvGBBxoAAAAJ&hl=en
https://www.signalintegrityjournal.com/authors/23-istvan-novak?page=2
The very small values in Table 2 of the National Semiconductor/TI document are presumably for packages that don't really have a lead frame, just very short vertical pieces of metal. The inductance is then completely dominated by the wire bonds, which are in Table 7. Flip-chip-like packages have neither wire bonds nor lead frames, so then you really get very low inductances.
Yeah, the x2y document is an oldie but a goodie, but the 4 terminal parts are not terribly useful IMO and dont actually present that much improvement over just using low inductance routing on a standard part. Using the x2y parts, with the recommended 6 vias takes up quite a bit of space in a layout and actually makes getting a cap nice and close to the pins more difficult. IMO its a gimmick and the package is counterproductive. I wanted to like them; the document reads well, but try and use them and you'll see what I mean.
Yes, I suppose you are right @KSTR and at least one of the output stage versions i'm using 1.5GHz opamps for IV, so RF and digital technique is advised especially. just a pet project to examine the use of more RF centric differential chips and their far superior packages, not because I have a pathological need for wide bandwidth. Yes, 6 layer pricing is hardly anything these days. hard gold edge connectors, HDI and via in pad (via in pad falls out of the HDI spec) are far more expensive options.
Hi all ... & thanks again for your many and constructive replies. A bit overwhelming though to really absorb this amount of information in a short while so I'll address what resonates (no pun intended) when reading through the posts and some of the links (and please also comment and post as you feel inclined and unrelated to my posts, etc.):
@Bonsai .. welcome to the discussion ...
The inductances of the DAC part pin measurement point (to the left of the V2_p) was taken from a package inductance specification document I think by Amkor. It is for an SSOP-28 package and the 3nH is the appr. inductance of the most distant pins (pin 1, 14, 15 & 28) of the package. However, as suggested by MarcelvdG I changed the inductances per pin to a 0.5x value due to their being placed next to a GND return pin on the IC in question (PCM1794). This is shown in the attachment in post #25.
And if I am not mistaken it is also indicated in the inductances of the package inductance link you provided (M12 values SSOP-28 - 1.45 nH). However, aside from the SSOP-28 package, some of the inductances are really low ... LLP, micro-SMD (CSP as I understand it) ... is this really realistic? Which IC's uses such packages BTW ... ?
@Markw4 : Thank you also for your feedbacks!
I don't remember reading it in the Ott book (could of course be elsewhere) but Rick Hartley has a couple of slides in a youtube video illustrating how reversing polarities on adjacent decoupling capacitors significantly reduces overall inductance. He is referencing Bruce Archambeault who apparently made such a study (could of course be others as well). I can post a link if anyone is interested ... ?
Thanks also for the links to the X2Y slides & the Istvan Novak links. TBH it is a bit much but I have read the X2Y slide and will also be reading some of the articles that appear interesting in the signal integrity journal.
@MarcelvdG : Knowing that you are quite well-versed in IC packages would you happen to know what the inductances of these packages would be? I think they are called US8 (case 846AN) and UQFN8 (CASE523AY):
https://www.onsemi.com/pdf/datasheet/nc7sz74-d.pdf
Although it probably is there somewhere I haven't been able to find this information searching the internet, so just if you happen to know about it ...
@InspectorGadget :
Interesting ... would you happen to know of a PCB manufacturing company (that is also humanly and environmentally fine) that has good prices for such 4 or 6 layer PCBs? I have been looking for some time now - and what I find typically is outside of my budget ...
And then a final comment which was spurred by Mark's X2Y link: How do you measure the response of a decoupling network in practice? In the X2Y slide link they mention three approaches listed from slides 9 - 16. Personally I would prefer to measure what happens when the circuitry is actually powered up but maybe this is not that easy ... any comments on how you do this?
Cheers & thanks again for some interesting feedbacks
Jesper
@Bonsai .. welcome to the discussion
...The inductances of the DAC part pin measurement point (to the left of the V2_p) was taken from a package inductance specification document I think by Amkor. It is for an SSOP-28 package and the 3nH is the appr. inductance of the most distant pins (pin 1, 14, 15 & 28) of the package. However, as suggested by MarcelvdG I changed the inductances per pin to a 0.5x value due to their being placed next to a GND return pin on the IC in question (PCM1794). This is shown in the attachment in post #25.
And if I am not mistaken it is also indicated in the inductances of the package inductance link you provided (M12 values SSOP-28 - 1.45 nH). However, aside from the SSOP-28 package, some of the inductances are really low ... LLP, micro-SMD (CSP as I understand it) ... is this really realistic? Which IC's uses such packages BTW ... ?
@Markw4 : Thank you also for your feedbacks!
I don't remember reading it in the Ott book (could of course be elsewhere) but Rick Hartley has a couple of slides in a youtube video illustrating how reversing polarities on adjacent decoupling capacitors significantly reduces overall inductance. He is referencing Bruce Archambeault who apparently made such a study (could of course be others as well). I can post a link if anyone is interested ... ?
Thanks also for the links to the X2Y slides & the Istvan Novak links. TBH it is a bit much but I have read the X2Y slide and will also be reading some of the articles that appear interesting in the signal integrity journal.
@MarcelvdG : Knowing that you are quite well-versed in IC packages would you happen to know what the inductances of these packages would be? I think they are called US8 (case 846AN) and UQFN8 (CASE523AY):
https://www.onsemi.com/pdf/datasheet/nc7sz74-d.pdf
Although it probably is there somewhere I haven't been able to find this information searching the internet, so just if you happen to know about it ...
@InspectorGadget :
Interesting ... would you happen to know of a PCB manufacturing company (that is also humanly and environmentally fine) that has good prices for such 4 or 6 layer PCBs? I have been looking for some time now - and what I find typically is outside of my budget ...
And then a final comment which was spurred by Mark's X2Y link: How do you measure the response of a decoupling network in practice? In the X2Y slide link they mention three approaches listed from slides 9 - 16. Personally I would prefer to measure what happens when the circuitry is actually powered up but maybe this is not that easy ... any comments on how you do this?
Cheers & thanks again for some interesting feedbacks
Jesper