The Well Tempered Master Clock - Group buy

[emyeuoi]

Ciao Andrea,

Would be interesting to understand if with 2 boards can be set as balanced output.

And just 2 x 3,3V for the whole dac... Nice board Andrea

Cheers,
Enrico

 

[andrea_mori]

Hi Enrico,

theoretically 2 boards should work as a balanced DAC but we have to check as soon the FIFO and the DAC are ready for test.

Andrea

 

[emyeuoi]

Thanks Andrea and congratulation... great job!

Cheers,
Enrico

 

[jmmbarco]

Hi Andrea!
So this DAC will work up to 24/192 with 5.6448 MHz and 6.144 MHz clocks??, however with those same clock speeds used in the FIFO you can only get 44.1/48 ??
Thank you

 

[andrea_mori]

Hi,

no, the DAC will work up to 24/192 with 5.6448 MHz and 6.144 MHz clocks installed in the FIFO Lite.

 

[jmmbarco]

Depending on the output DAC max. sample rate will be different then? I have 5.6448 MHz and 6.144 MHz plus two doublers to get 88.2/96 into a TDA1541, am I wrong?

 

[lasercut]

TDA1541 is only a 16bit dac

176.4kHz x 16bit x 2 channels = 5.6448 MHz WCLK, no doubler needed up to 176kHz.

Does TDA1541 have a mode with parallel data input? then you might get up to 352.8kHz, I'm not sure.

 

[andrea_mori]

In simultaneous mode and stopped clock you can drive the TDA1541A up to 192kHz with 5.6448 MHz and 6.144 MHz oscillators (16 bit x 192kHz sample rate x 2 stopped clock = 6.144MHz).
I believe this is the best way to drive the TDA.

 

[jmmbarco]

Thank you lasercut and Andrea! I was wrong because I considered 24/96 (CS8414 input) instead 16 which is the real resolution of TDA...
Sorry, I know it is quite off-topic here but I just don´t really understand how simultaneous mode works and I cannot find a non-confusing explanation anywhere
In I2S mode and BCK running at 6.144Mhz and WS 192khz you get 32 bits of L+R channels. In the LOW part of the WS period you get 16 bits of left channel and when in HIGH you get the other 16 bits of the right one. Ok so far.
Now in simultaneous, both L & R are read at the same time on one falling edge of BCK, so true bitrate should be doubled but if the rising edge of LE signal indicates sample at output, and there is only one rising edge per period, how can bitrate can be actually doubled???

I mean it is true that L+R are read simultaneously but if LE frequency signal is not doubled, how can 384 be achieved?? Again only one L+R sample is read in a LE period...

 

[andrea_mori]

You can achieve 384 kHz in continuous mode clock:
16 bit x 384kHz sample rate = BCK 6.144 MHz.

But I would use stopped clock mode so to achieve 384kHz you need:
16 bit x 384kHz sample rate x 2 stopped clock = 12.244MHz

 

[exeric]

Andrea,
Will you be doing another group buy that includes the drixo oscillators and STS boards of the last group buy? Of course, that would include another round of oscillator group buys also.

 

[andrea_mori]

Yes, I will start a new GB as soon as the FIFO and the DAC Lite are ready.

It will include all the items of the previous GB, crystals, oscillators, doublers, STS and so on.

 

[Blitz]

Nice...looking forward to try your FIFO+DAC-Lite...so we have a DAC and FIFO now for your clocks...cant wait to compare your combo with my Soekris-1941 setup.

Maybe you can offer an option without soldered resistors ? So anyone can make his own choices on resistor quality.

I believe I de-soldered about 100 ceramic SMD caps from the Soekris before it sounded good...glad that I do not see so many of these little devils on your prototype.

 

[andrea_mori]

The DAC board without the ladder resistors could be an option, although we have implemented a digital calibration in the FIFO Lite so even 0.1% resistors should work fine once calibrated.

 

[Blitz]

I think more about different materials like tantalum resistors etc...I think that has been discussed around this thread: Signalyst DSC1

If I recall right, PAvel had even preferences on the shift register chips like NOS Philips sounded best...

 

[andrea_mori]

Ah ok, the only problem could be the resistors footprint, the DAC Lite provides 0805 footprint.

About the shift registers we don't use the 595, we use single flip-flop for each bit.

 

[Abra]

10 MHz clock is available?

 

[exeric]

My understanding is that there is a minimum quantity that needs to be ordered. I'm interested in the 10 Mhz SC crystal also so we'll just have to get at least 10 or so orders for them.

 

[Abra]

OK, I need 2 pcs. Anybody else?

 

[anatech]

Let me know what we are looking at please.