It handles capacitive loads very well without inductor. Some power loss from the resistor though.
Why would you want to compensate it differently, its very near perfect ?
There was some varience in compensation during the production life but nothing major.
Just to rekindle my memory I simmed the amp as well, as expected the ULGF was 2.4 Mhz, actually very close to 2.5MHZ.
ULGF 2.3 Mhz. Not much in it compaired to LT.
I wonder how you can be as far off as 1.25 Mhz ??
Give me a day or two and Ill post my results.
If it s the schematic he posted the previous page it is obvious
why he didnt get the same results as yours....
Should he reduce the VAS degeneration resistors from his bizzare
100R value to 50 or 33R that he would see the ULGF raising substancialy
up to the values you quoted.
Also , he used a relatively high CLG figure , wich will only reduce
ULGF further...
I should have trusted my instinct, thanks I missed that
I was already suspicious looking at his posted result as the crossing seems to be in the centre between 1 and 5 Mhz (I assumed 2.5Mhz) although the result states 1.25Mhz. I was thinking he doctored the stated result.
Sorry Wahab, misunderstanding, we want to establish the ULGF of the cyrus as per schematic. So Walys 100ohm is correct. We talking here of a difference of more than 1MHZ.
Wich Cyrus.?.Is there a schematic that was posted.?.
Edit : Actualy Waly s schematic is the one he posted earlier in PDF ,
with said 100R i get 1.5MHz ULGF , i ll recheck with the models
used in the actual schematic but i dont think it will make
a big difference unless i missed something.
Last edited:
What are our other choices, in regard with DC offset ?
Servo ?
I think It brings complexity and its own evils as well. At least, In VSSA, the lytic is not directly in the signal path and has a limited action on the overall gain as it reduce only the DC input gain.
Well, we could try higher values to minimize the group delay error...
Any idea about the way can sound supercaps here ?
It is in the feedback path(and that is signal path) and if can do without it's much better.
1- It is in // with the CCS, so reduced influence, means only on the little gain range of the input stage, right ?
If this cap has infinite impedance, or is removed, the input stage will still have a 1 gain, right ?
Not as bad as the cap in the ground return of my amp feedback network.
2- Yes, of course.
Last edited:
Maybe you dont have models for the transistors used but I do and yes they are available. Im will sell them to you if you interested. They are not cheap at all but I as user and the company that produced them can gaurantee their conformity to the highest level. You just need to supply the batch production number for best model matching.
As I dont trust simulation that much I repeated using a different simulation program, Multisim. ULGF 2.3 Mhz. Not much in it compaired to LT.
I wonder how you can be as far off as 1.25 Mhz ??
Uh, oh. So (i) you have the device models in the original Cyrus schematic that I posted here, (ii) you won't share them so that everybody could reproduce your results (but offer them for sale!), (iii) although these devices (according to the data sheets) are clearly inferior (in Ft, Beta, VA, etc...) to the modern devices I used in simulation, you get double the ULGF. Again, without any possibility to cross check the results.
You failed again to provide any shred of credible information.
Yes, I captured the schematic in the original Cyrus PDF I posted here. 1.5MHz ULGF sounds more credible. If you can get the models for the devices in the original schematic (other than the IMZ1A PNP/NPN dual, which is available on the Rohm web site), let me know. I would expect them to have a significant impact in lowering the ULGF (for the reasons I already mentioned).
I re-did the simulation using the IMZ1A models and the BC/BD per the original schematic. Unfortunately the models for the VAS, pre-drivers, drivers and output devices are not available for free. I cannot afford to pay manso for the models (thank you for the offer, though), so I used the same devices as before (again, according to the data sheets, all much better in performance compared to the originals).
This time I got 1.3MHz ULGF, that is about the same as in the previous simulation (1.25MHz). Not unexpected, as the input devices do not have a huge impact on the ULGF - the VAS device and the drivers/outputs do. This time I included the log scale grid in the GP plot, for manso's reading convenience.
EDIT: BTW, Bonsai is correct. Without an output inductor, the (local) stability of the output triple in capacitive loads is dangerously low: only 4 degrees phase margin for a 100nF load (see attachment).
I would though expect this phase margin to be larger for the original devices, as they are significantly slower than the ones I used in this simulation exercise.
This time I got 1.3MHz ULGF, that is about the same as in the previous simulation (1.25MHz). Not unexpected, as the input devices do not have a huge impact on the ULGF - the VAS device and the drivers/outputs do. This time I included the log scale grid in the GP plot, for manso's reading convenience.
EDIT: BTW, Bonsai is correct. Without an output inductor, the (local) stability of the output triple in capacitive loads is dangerously low: only 4 degrees phase margin for a 100nF load (see attachment).
I would though expect this phase margin to be larger for the original devices, as they are significantly slower than the ones I used in this simulation exercise.
Attachments
Last edited:
Considering the advantages and simplicity to have independant OPS bias (VSSA like) any advantage using a CCS in VAS too ?
Or, instead of the input CSS ?
I think I know what's happening here... Manso (and he's not alone in this confusion) is looking in simulation at the open loop gain, which indeed has a crossover frequency of about 2.4MHz (with the best devices/models).
However, this has little to do with what really matters (for distortions, stability, etc...) which are the loop gain and the Unity Loop Gain Frequency (which is 1.3MHz). Only at low frequencies the difference is loop gain = open loop gain - closed loop gain. (which is also obvious if you visually compare the graph attached to this post to the previous, 66dB (LF loop gain) =100dB (LF open loop gain) - 34dB (LF closed loop gain).
See the attachment for the open loop gain results.
However, this has little to do with what really matters (for distortions, stability, etc...) which are the loop gain and the Unity Loop Gain Frequency (which is 1.3MHz). Only at low frequencies the difference is loop gain = open loop gain - closed loop gain. (which is also obvious if you visually compare the graph attached to this post to the previous, 66dB (LF loop gain) =100dB (LF open loop gain) - 34dB (LF closed loop gain).
See the attachment for the open loop gain results.
Attachments
What about this (because I don't like those caps at all): http://www.diyaudio.com/forums/solid-state/240712-cfa-topology-audio-amplifiers-86.html#post3620043
The OPS devices are 15 MHz Ft only but slower power devices will hardly
decrease the ULGF since the drivers and pre drivers will still have tremendous
beta in the vicinity of this frequency , about 10k is likely , hence even using
MJL21193/21194 will only shift said frequency from 1.6 to 1.4MHz.
Of course in large signal mode the drivers would explode quickly
if ever such high frequency is tested with a 8R load.
Hi Belaji,
Halas, as-it, it shows 0.090633% distortion at 1KHz 50W, while VSSA has 0.000839%. Same OPS, 150mA bias.
I just did a sim on it. (Is-it good enough for comparing ?).
Halas, as-it, it shows 0.090633% distortion at 1KHz 50W, while VSSA has 0.000839%. Same OPS, 150mA bias.
Last edited:
It's surprising that decreasing the OP devices Ft from 30MHz to 4 MHz affects the ULGF by 200 KHz only, however the TIS/VAS device Early voltage (and Cob) will probably have a significantly larger effect. You are not using the MJL21193/94 Onsemi models, right?
Result will be the same for whatever device wich has a Ft
higher than the ULGF , at 1-2MHz see the final power transistors
as simple buffers with a beta of 1 or so with the pre drivers + drivers
able to provide a beta high enough such that the previous stage is not
significantly loaded , at least in a small signal analysis as once the output
amplitude is in large signal mode the drivers will provide the full output
current since the final stage has beta of 1.
For the same reason the lower FT devices will decrease the amplifier
gain significantly once Ft is approached , at about 2.5MHz for 4MHz Ft
devices , i tested with a few ones to check the reproducibility.
The low ULGF variation is a hint that the amplifier caracteristic
frequency reponse wise is firstly determined by the shunt compensation
as well as by the VAS degeneration.
Wanna post one of YOUR designs with performance us old fogeys can only dream off?
Us oldies are never too old to learn from true gurus
I am not gurus, may be Bob could help with his cfa design.
My CFA is just asymetrical with each has own feedback. One feedback to adjust the sound and cancel oscillation and another high feedback for error correction.
This is my error correcting feedback sceme actually it is common (half / one feedback). The compensations could be used as it is typical topology.
