Pondering this further, If I run square wave sims into various capacitive loads, it looks to be stable. However, if I run a Loop Gain sim using the Tian method I can see the erosion of margin, even if I add a small inductor to account for the the self inductance of the wiring. Is simulating capacitive loading with the Tian Probe method reliable? I've never thought to look at it that way. I've used square wave testing to assess this.
chorus?, flanger?, phase shifter,? tremolo?, vibrato?honestly, I do not know...
I don’t think it will be possible to check anything with this solution, we need to think about it...
unity gain frequency 29 MHz !?!?, with “jump” in Pi/2 and + 60 degrees. !?!?
Perhaps I have some incorrect element models. But they haven't let me down yet...
at high frequencies on the drains Q1.1 and Q1.2. the common-mode signal is summed at the B-E of transistor Q3.
everyone uses this method and you it shows that nothing happens, so I think that we have different models of transistors.
Some progress to report…
I’ve spend considerable time in simulations refining the design with practical concerns in mind. Some of the goals that I’ve tried to attain are:
User benpe has been helping with the design process. He has been patiently working with me, providing feedback on the schematics and boards, and has graciously offered to be rat lab #1. His initial build is complete, and it plays music without letting any magic smoke out. No critical listening or testing completed. The testing he’s completed so far has validated results from simulations.
My build is under way, but is still a few weeks out.
A design goal of mine was to maximize the class A region while using a 2U heatsink. To help in realizing this, the design uses separate rails for the IPS/VAS (V2 PSU) and OPS (V1 PSU) with the V2 PSU running 6 volts above the V1 PSU. This allows for higher output without increased dissipation. And the higher IPS-VAS rails drop distortion a bit. Benpe’s implementation uses separate PSUs to accomplish this. However, I have designed the boards with a provision for rail boosting, that only requires a single PSU. The boards have options that let the builder decide if they want to use a completely separate PSU (like Benpe), or if they what to use my rail boosting concept... or no rail boost and run off of one voltage.
This V2 PSU boost concept uses isolated DC-DC converters with the output ground referenced to the V1 rails. This boosts the rails by 12V, and then runs them through an aggressive RC filter dropping the final boost to 6V. The result is boosted rails with a high PSRR. This has been tested on breadboard, but still needs final testing in my build. The concept is not mine – I first saw it described in Winfield Hill’s AMP-70 laboratory amplifier.
Benpe’s build uses 24V V1rails and 29V V2 rails in a 3U chassis. This should be good for 25W with a 6W class A region. He’s done initial testing at 560mA of bias with the heatsinks settling in at 50C. This agrees with simulations. My build will use a 2U chassis with 30V V1 rails and 36V V2 rails for 40W into 8R with the same 6W class A region.
We are working on a detailed build guide. It’s still a work in progress that needs additional refinement with results from further testing on the bench. I’ll release all the details once we have the design more thoroughly tested.
Finally, I am referring to this version as the “Ultra +P”. The +P indicating the additional power from the higher rail voltages than lineup’s originally proposed design.
It’s been a fun project. Thanks to Lineup for the design! Simple but clever.
The build pics attached are from my build.
I’ve spend considerable time in simulations refining the design with practical concerns in mind. Some of the goals that I’ve tried to attain are:
- Simple design that favors lower order harmonics.
- High slew rate with soft clipping behavior
- Thermally stable, with DC offset and bias that vary as little as possible between cold and hot states and/or with power supply fluctuations.
- A design that accounts for variability in actual devices vs models used in simulation.
- High Class A region that works within a 2U or 3U chassis.
User benpe has been helping with the design process. He has been patiently working with me, providing feedback on the schematics and boards, and has graciously offered to be rat lab #1. His initial build is complete, and it plays music without letting any magic smoke out. No critical listening or testing completed. The testing he’s completed so far has validated results from simulations.
My build is under way, but is still a few weeks out.
A design goal of mine was to maximize the class A region while using a 2U heatsink. To help in realizing this, the design uses separate rails for the IPS/VAS (V2 PSU) and OPS (V1 PSU) with the V2 PSU running 6 volts above the V1 PSU. This allows for higher output without increased dissipation. And the higher IPS-VAS rails drop distortion a bit. Benpe’s implementation uses separate PSUs to accomplish this. However, I have designed the boards with a provision for rail boosting, that only requires a single PSU. The boards have options that let the builder decide if they want to use a completely separate PSU (like Benpe), or if they what to use my rail boosting concept... or no rail boost and run off of one voltage.
This V2 PSU boost concept uses isolated DC-DC converters with the output ground referenced to the V1 rails. This boosts the rails by 12V, and then runs them through an aggressive RC filter dropping the final boost to 6V. The result is boosted rails with a high PSRR. This has been tested on breadboard, but still needs final testing in my build. The concept is not mine – I first saw it described in Winfield Hill’s AMP-70 laboratory amplifier.
Benpe’s build uses 24V V1rails and 29V V2 rails in a 3U chassis. This should be good for 25W with a 6W class A region. He’s done initial testing at 560mA of bias with the heatsinks settling in at 50C. This agrees with simulations. My build will use a 2U chassis with 30V V1 rails and 36V V2 rails for 40W into 8R with the same 6W class A region.
We are working on a detailed build guide. It’s still a work in progress that needs additional refinement with results from further testing on the bench. I’ll release all the details once we have the design more thoroughly tested.
Finally, I am referring to this version as the “Ultra +P”. The +P indicating the additional power from the higher rail voltages than lineup’s originally proposed design.
It’s been a fun project. Thanks to Lineup for the design! Simple but clever.
The build pics attached are from my build.
Attachments
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Why not use v6 classic opamp as ips and lateral mosfet as ops?
https://www.bursonaudio.com/products/supreme-sound-opamp-v6/
https://www.bursonaudio.com/products/supreme-sound-opamp-v6/
Simplicity. I wanted to honor Lineup's idea and keep it simple. I'm sure there's a thousand different ways this could be reimagined, but most will add parts. I make no claims that its the best or couldn't be "better". This is the way I choose to build it, given my objectives.
It's been a fun project. And for a hobby, this part is important
It's been a fun project. And for a hobby, this part is important
Another reference I forgot to mention - For Lateral MOSFET stability, the ideas from this thread are used: Revisiting lateral MOSFET stability
From the thread referenced in post 170. Simulations do not reveal any issues. But I've seen several threads mention stability issues with Exicon Laterals, and these gate to drain caps seem to resolve them. Adding them in simulations didn't seem to degrade anything, so I'm suggesting to add them. Until one of us tests without them to see if any issues arise.
Hi Lineup,
Your design has some key differences from mine. I'd like to explain why I chose different values.
Your design has some key differences from mine. I'd like to explain why I chose different values.
- Gain: You design has a higher gain. I choose to lower the gain with more feedback to address distortion that was rising rapidly with frequency. I suspect your THD sims are all at 1kHz. Try looking at 10kHz and 20kHz to see how more feedback affects it.
- VAS Current: Similar to #1, more VAS current helps at higher frequencies.
- IPS Current: I'm suggesting 1mA because this seem to be the NULL tempco point for LSK489/KSJ689. You get a bit less slew rate, but more temperature stability. You'll see Linear's and Bob Cordell's design notes using this current It's not explicitly stated, but I suspect this is the reason. I also have degeneration on the P channel to address gain mismatches between the P and N channels at 1mA. Linear and Bob Cordell both discuss this.
- MOSFET gate stoppers: I'm using higher values as well as caps across the gate to drain. This is to address stability concerns that arise in practice. Simulations WILL NOT reveal this. Many builds on these forums using Exicon devices all discuss this issue. The solution if higher gate stoppers and caps across the gate and drain. Take a look at the thread I referenced in post #170.
- Device models: Since this is a simple design, it's sensitive to parts selection. Especially the VAS. What models are you using for the VAS? Are they D or E grade? This makes a big difference. Benpe and I are both using NOS SC3503E/SA1381E for our testing. These are out of production parts. I'll be testing later with in production SC3503D/SA1381E. Based on sims, the gain mismatch on these will cause DC offset in the 30 to 50mV range. I plan to address this using different resistor values to N vs P sides. My sims tested with models from Bob Cordell and Cabirio (found here). In addition, I modded these models to adjust the gains to see how it affects DC offset and OPS bias stability with regard to temperature.
- Feedback Cap: Your design lacks a feedback cap. I'm assuming you are not running temperature and voltage variance sims. I found that a feedback cap is needed to guard against DC offset changes that occur with temp and voltage changes that will occur in the real world.
- Miller Caps: You are running much higher values. With my 15p caps, I'm getting 25db and 65 degrees of margin on Loop Gain analysis. Can I ask why you values are so much higher? The margins I am getting seem high enough for stability.
- Higher Rails: I'm running higher rails to allow for a 25W region that is out of clipping and has good performance. If you look at the graph I attached in post 166, you can see that distortion climbs much quicker after 25W. Also, 24V to 30V main rails seem to offer the best economy with a 2U chassis, allowing the design to make full use of the heatsinks without running too hot.
- Output networks: Your design does not have a Zobel or Theile network on the output.
Hi Gannaji,
I don't have a single sim file or single set of models. I used several models in addition to my own tweaks to some of the models. This is to account for the real world, where devices will vary between builders. But I'll see if I can clean them up and post something here.
For my and benpe's initial builds, we are both using SC3503E/SA1381E for the VAS. The E grade SC3503 are out of production. We've each tested our devices and the gains seem to be similar. This was incorporated into the sims. I plan to also test SC3503D/SA1381E, TT004B/TTA004B and BD139/BD140. The R4/R5 and R8/R9 resistors will be different for each combination... the price you pay for a simple design. A two transistor VAS (four in total) would guard against this, but would also alter the design considerably.
One aspect that isn't clear yet is if the Idss value of the N and P channels should ideally be matched or if it doesn't matter. Also, if Idss varys between 4mA and 8mA, does it matter where your devices fall in the range. I have a range of JFETs to test with. I hope to eventually answer this. The available models are limited, so its hard to explore this in sims.
LTSpice simulation files attached. These sims match the VAS devices we are using in the test build (SC3503E / SA1381E). The JFET models are in the 5 - 6 mS Idss range. This is in similar to what we are using for the test builds. We are both using TO-247 package Exicons for the Lateral MOSFETS.
Dear community,
With the great help from @brian92fs I have completed my both boards today.
My goal was to build integrated amplifier so anyway power supply was different from brian92fs' idea.
I have build OPS PS on one transformer, two diode bridges and capacitors providing +/-24V.
For IPS/VAS there is a shunt regulated PS with +/- 29V.
For the preamp section I needed remote control, display and nice volume control, I have decided to go with aliexpress' MUSES72320 board (4 inputs, two double op-amps, OLED display, remote). I have reworked power supply for this preamp board.
I have used standard modushop's amp 3U case.
Soft start is from h9kpxg.
In a week or two I will arrange measurements (THD, bandwidth, etc).
Thank you brian92fs, thank you lineup.
Please do not hate me for the cabling, I will do some rework, today my priority was to get some sound and I got it.
With the great help from @brian92fs I have completed my both boards today.
My goal was to build integrated amplifier so anyway power supply was different from brian92fs' idea.
I have build OPS PS on one transformer, two diode bridges and capacitors providing +/-24V.
For IPS/VAS there is a shunt regulated PS with +/- 29V.
For the preamp section I needed remote control, display and nice volume control, I have decided to go with aliexpress' MUSES72320 board (4 inputs, two double op-amps, OLED display, remote). I have reworked power supply for this preamp board.
I have used standard modushop's amp 3U case.
Soft start is from h9kpxg.
In a week or two I will arrange measurements (THD, bandwidth, etc).
Thank you brian92fs, thank you lineup.
Please do not hate me for the cabling, I will do some rework, today my priority was to get some sound and I got it.
